forked from OSchip/llvm-project
Set the default hardware division features for ARM cpus. Also set it as default for A32 armv8.
llvm-svn: 193075
This commit is contained in:
Silviu Baranga
parent
f9671dd09d
commit
e5690463e2
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@ -3760,16 +3760,31 @@ public:
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}
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void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
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StringRef ArchName = getTriple().getArchName();
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if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
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Features["vfp2"] = true;
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else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
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CPU == "cortex-a9-mp") {
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Features["vfp3"] = true;
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Features["neon"] = true;
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} else if (CPU == "swift" || CPU == "cortex-a5" ||
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CPU == "cortex-a7" || CPU == "cortex-a15") {
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}
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else if (CPU == "cortex-a5") {
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Features["vfp4"] = true;
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Features["neon"] = true;
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} else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a15") {
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Features["vfp4"] = true;
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Features["neon"] = true;
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Features["hwdiv"] = true;
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Features["hwdiv-arm"] = true;
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} else if (CPU == "cortex-r5" || CPU == "cortex-a53"||
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CPU == "cortex-a57" || CPU == "cortex-m3" ||
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CPU == "cortex-m4" ||
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// Enable the hwdiv extension for all v8a AArch32 cores by
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// default.
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ArchName == "armv8a" || ArchName == "armv8" ||
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ArchName == "thumbv8a" || ArchName == "thumbv8") {
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Features["hwdiv"] = true;
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Features["hwdiv-arm"] = true;
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}
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}
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@ -9,3 +9,129 @@
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// CHECK-V7: __ARM_ARCH 7
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// CHECK-V7: __ARM_ARCH_7A__ 1
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// CHECK-NOT-V7: __ARM_FEATURE_CRC32
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// Check that -mhwdiv works properly for armv8/thumbv8 (enabled by default).
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// RUN: %clang -target armv8 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8 %s
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// ARMV8:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8 -mthumb -x c -E -dM %s -o - | FileCheck --check-prefix=THUMBV8 %s
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// THUMBV8:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8-eabi -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-EABI %s
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// ARMV8-EABI:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8-eabi -mthumb -x c -E -dM %s -o - | FileCheck --check-prefix=THUMBV8-EABI %s
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// THUMBV8-EABI:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8 -mhwdiv=none -x c -E -dM %s -o - | FileCheck --check-prefix=NONEHWDIV-ARMV8 %s
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// NONEHWDIV-ARMV8-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target armv8 -mthumb -mhwdiv=none -x c -E -dM %s -o - | FileCheck --check-prefix=NONEHWDIV-THUMBV8 %s
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// NONEHWDIV-THUMBV8-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target armv8 -mhwdiv=thumb -x c -E -dM %s -o - | FileCheck --check-prefix=THUMBHWDIV-ARMV8 %s
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// THUMBHWDIV-ARMV8-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target armv8 -mthumb -mhwdiv=arm -x c -E -dM %s -o - | FileCheck --check-prefix=ARMHWDIV-THUMBV8 %s
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// ARMHWDIV-THUMBV8-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target armv8a -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8A %s
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// ARMV8A:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8a -mthumb -x c -E -dM %s -o - | FileCheck --check-prefix=THUMBV8A %s
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// THUMBV8A:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8a-eabi -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8A-EABI %s
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// ARMV8A-EABI:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8a-eabi -x c -E -dM %s -o - | FileCheck --check-prefix=THUMBV8A-EABI %s
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// THUMBV8A-EABI:#define __ARM_ARCH_EXT_IDIV__ 1
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// Test that -mhwdiv has the right effect for a target CPU which has hwdiv enabled by default.
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// RUN: %clang -target armv7 -mcpu=cortex-a15 -x c -E -dM %s -o - | FileCheck --check-prefix=DEFAULTHWDIV-ARM %s
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// DEFAULTHWDIV-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-a15 -x c -E -dM %s -o - | FileCheck --check-prefix=DEFAULTHWDIV-THUMB %s
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// DEFAULTHWDIV-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv7 -mcpu=cortex-a15 -mhwdiv=arm -x c -E -dM %s -o - | FileCheck --check-prefix=ARMHWDIV-ARM %s
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// ARMHWDIV-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-a15 -mhwdiv=thumb -x c -E -dM %s -o - | FileCheck --check-prefix=THUMBHWDIV-THUMB %s
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// THUMBHWDIV-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target arm -mcpu=cortex-a15 -mhwdiv=thumb -x c -E -dM %s -o - | FileCheck --check-prefix=DEFAULTHWDIV-THUMBHWDIV-ARM %s
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// DEFAULTHWDIV-THUMBHWDIV-ARM-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target arm -mthumb -mcpu=cortex-a15 -mhwdiv=arm -x c -E -dM %s -o - | FileCheck --check-prefix=DEFAULTHWDIV-ARMHWDIV-THUMB %s
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// DEFAULTHWDIV-ARMHWDIV-THUMB-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target arm -mcpu=cortex-a15 -mhwdiv=none -x c -E -dM %s -o - | FileCheck --check-prefix=DEFAULTHWDIV-NONEHWDIV-ARM %s
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// DEFAULTHWDIV-NONEHWDIV-ARM-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target arm -mthumb -mcpu=cortex-a15 -mhwdiv=none -x c -E -dM %s -o - | FileCheck --check-prefix=DEFAULTHWDIV-NONEHWDIV-THUMB %s
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// DEFAULTHWDIV-NONEHWDIV-THUMB-NOT:#define __ARM_ARCH_EXT_IDIV__
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// FIXME: add check for further predefines
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// Test whether predefines are as expected when targeting cortex-a5.
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// RUN: %clang -target armv7 -mcpu=cortex-a5 -x c -E -dM %s -o - | FileCheck --check-prefix=A5-ARM %s
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// A5-ARM-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-a5 -x c -E -dM %s -o - | FileCheck --check-prefix=A5-THUMB %s
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// A5-THUMB-NOT:#define __ARM_ARCH_EXT_IDIV__
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// Test whether predefines are as expected when targeting cortex-a8.
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// RUN: %clang -target armv7 -mcpu=cortex-a8 -x c -E -dM %s -o - | FileCheck --check-prefix=A8-ARM %s
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// A8-ARM-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-a8 -x c -E -dM %s -o - | FileCheck --check-prefix=A8-THUMB %s
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// A8-THUMB-NOT:#define __ARM_ARCH_EXT_IDIV__
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// Test whether predefines are as expected when targeting cortex-a9.
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// RUN: %clang -target armv7 -mcpu=cortex-a9 -x c -E -dM %s -o - | FileCheck --check-prefix=A9-ARM %s
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// A9-ARM-NOT:#define __ARM_ARCH_EXT_IDIV__
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-a9 -x c -E -dM %s -o - | FileCheck --check-prefix=A9-THUMB %s
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// A9-THUMB-NOT:#define __ARM_ARCH_EXT_IDIV__
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// Test whether predefines are as expected when targeting cortex-a15.
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// RUN: %clang -target armv7 -mcpu=cortex-a15 -x c -E -dM %s -o - | FileCheck --check-prefix=A15-ARM %s
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// A15-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-a15 -x c -E -dM %s -o - | FileCheck --check-prefix=A15-THUMB %s
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// A15-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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// Test whether predefines are as expected when targeting swift.
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// RUN: %clang -target armv7s -mcpu=swift -x c -E -dM %s -o - | FileCheck --check-prefix=SWIFT-ARM %s
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// SWIFT-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv7s -mthumb -mcpu=swift -x c -E -dM %s -o - | FileCheck --check-prefix=SWIFT-THUMB %s
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// SWIFT-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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// Test whether predefines are as expected when targeting cortex-a53.
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// RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-ARM %s
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// A53-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-THUMB %s
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// A53-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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// Test whether predefines are as expected when targeting cortex-r5.
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// RUN: %clang -target armv7 -mcpu=cortex-r5 -x c -E -dM %s -o - | FileCheck --check-prefix=R5-ARM %s
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// R5-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-r5 -x c -E -dM %s -o - | FileCheck --check-prefix=R5-THUMB %s
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// R5-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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// Test whether predefines are as expected when targeting cortex-m0.
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-m0 -x c -E -dM %s -o - | FileCheck --check-prefix=M0-THUMB %s
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// M0-THUMB-NOT:#define __ARM_ARCH_EXT_IDIV__
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// Test whether predefines are as expected when targeting cortex-m3.
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-m3 -x c -E -dM %s -o - | FileCheck --check-prefix=M3-THUMB %s
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// M3-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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// Test whether predefines are as expected when targeting cortex-m4.
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// RUN: %clang -target armv7 -mthumb -mcpu=cortex-m4 -x c -E -dM %s -o - | FileCheck --check-prefix=M4-THUMB %s
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// M4-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
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