forked from OSchip/llvm-project
[X86][SSE] Added tests showing missed truncations for sitofp conversion
SelectionDAG::ComputeNumSignBits is poor at build_vector handling, meaning that we can't see that all the vXi64 sources are in fact sign extended i32 or smaller. llvm-svn: 297486
This commit is contained in:
Simon Pilgrim
parent
bc97ab28a4
commit
e54cd65399
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@ -0,0 +1,109 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
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define <2 x double> @signbits_sext_v2i64_sitofp_v2f64(i32 %a0, i32 %a1) nounwind {
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; X32-LABEL: signbits_sext_v2i64_sitofp_v2f64:
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; X32: # BB#0:
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; X32-NEXT: pushl %ebp
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $32, %esp
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; X32-NEXT: movl 8(%ebp), %eax
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; X32-NEXT: movl 12(%ebp), %ecx
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; X32-NEXT: vmovd %eax, %xmm0
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; X32-NEXT: sarl $31, %eax
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; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
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; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: vmovd %ecx, %xmm0
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; X32-NEXT: sarl $31, %ecx
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; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
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; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: fildll {{[0-9]+}}(%esp)
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; X32-NEXT: fstpl {{[0-9]+}}(%esp)
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; X32-NEXT: fildll {{[0-9]+}}(%esp)
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; X32-NEXT: fstpl (%esp)
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; X32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X32-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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;
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; X64-LABEL: signbits_sext_v2i64_sitofp_v2f64:
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; X64: # BB#0:
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; X64-NEXT: vcvtsi2sdl %esi, %xmm0, %xmm0
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; X64-NEXT: vcvtsi2sdl %edi, %xmm1, %xmm1
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; X64-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; X64-NEXT: retq
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%1 = sext i32 %a0 to i64
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%2 = sext i32 %a1 to i64
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%3 = insertelement <2 x i64> undef, i64 %1, i32 0
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%4 = insertelement <2 x i64> %3, i64 %2, i32 1
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%5 = sitofp <2 x i64> %4 to <2 x double>
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ret <2 x double> %5
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}
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define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext %a1, i32 %a2, i32 %a3) nounwind {
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; X32-LABEL: signbits_sext_v4i64_sitofp_v4f32:
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; X32: # BB#0:
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; X32-NEXT: pushl %ebp
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: pushl %esi
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $56, %esp
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; X32-NEXT: movsbl 8(%ebp), %eax
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; X32-NEXT: movswl 12(%ebp), %ecx
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; X32-NEXT: movl 16(%ebp), %edx
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; X32-NEXT: movl 20(%ebp), %esi
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; X32-NEXT: vmovd %eax, %xmm0
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; X32-NEXT: sarl $31, %eax
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; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
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; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: vmovd %ecx, %xmm0
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; X32-NEXT: sarl $31, %ecx
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; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
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; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: vmovd %edx, %xmm0
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; X32-NEXT: sarl $31, %edx
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; X32-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
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; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: vmovd %esi, %xmm0
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; X32-NEXT: sarl $31, %esi
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; X32-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
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; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: fildll {{[0-9]+}}(%esp)
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; X32-NEXT: fstps {{[0-9]+}}(%esp)
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; X32-NEXT: fildll {{[0-9]+}}(%esp)
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; X32-NEXT: fstps {{[0-9]+}}(%esp)
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; X32-NEXT: fildll {{[0-9]+}}(%esp)
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; X32-NEXT: fstps {{[0-9]+}}(%esp)
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; X32-NEXT: fildll {{[0-9]+}}(%esp)
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; X32-NEXT: fstps (%esp)
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; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; X32-NEXT: leal -4(%ebp), %esp
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; X32-NEXT: popl %esi
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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;
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; X64-LABEL: signbits_sext_v4i64_sitofp_v4f32:
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; X64: # BB#0:
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; X64-NEXT: vmovd %edi, %xmm0
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; X64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
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; X64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
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; X64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
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; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X64-NEXT: retq
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%1 = sext i8 %a0 to i64
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%2 = sext i16 %a1 to i64
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%3 = sext i32 %a2 to i64
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%4 = sext i32 %a3 to i64
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%5 = insertelement <4 x i64> undef, i64 %1, i32 0
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%6 = insertelement <4 x i64> %5, i64 %2, i32 1
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%7 = insertelement <4 x i64> %6, i64 %3, i32 2
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%8 = insertelement <4 x i64> %7, i64 %4, i32 3
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%9 = sitofp <4 x i64> %8 to <4 x float>
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ret <4 x float> %9
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}
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