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[SPARC] Enable writing to floating-point-state register. 

llvm-svn: 245475
This commit is contained in:
Douglas Katzman 2015-08-19 18:34:48 +00:00
parent 596aec96ac
commit e5485c651e
5 changed files with 43 additions and 0 deletions
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9
llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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@ -772,6 +772,9 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
case Sparc::PSR:
Op = SparcOperand::CreateToken("%psr", S);
break;
case Sparc::FSR:
Op = SparcOperand::CreateToken("%fsr", S);
break;
case Sparc::WIM:
Op = SparcOperand::CreateToken("%wim", S);
break;
@ -898,6 +901,12 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
return true;
}
if (name.equals("fsr")) {
RegNo = Sparc::FSR;
RegKind = SparcOperand::rk_Special;
return true;
}
if (name.equals("wim")) {
RegNo = Sparc::WIM;
RegKind = SparcOperand::rk_Special;

16
llvm/lib/Target/Sparc/SparcInstrInfo.td
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@ -434,6 +434,22 @@ let DecoderMethod = "DecodeLoadQFP" in
defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
Requires<[HasV9, HasHardQuad]>;
let DecoderMethod = "DecodeLoadFP" in
let Defs = [FSR] in {
let rd = 0 in {
def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
"ld [$addr], %fsr", []>;
def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
"ld [$addr], %fsr", []>;
}
let rd = 1 in {
def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
"ldx [$addr], %fsr", []>, Requires<[HasV9]>;
def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
"ldx [$addr], %fsr", []>, Requires<[HasV9]>;
}
}
// Section B.4 - Store Integer Instructions, p. 95
let DecoderMethod = "DecodeStoreInt" in {
defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;

2
llvm/lib/Target/Sparc/SparcRegisterInfo.td
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@ -60,6 +60,8 @@ def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
foreach I = 0-3 in
def FCC#I : SparcCtrlReg<I, "FCC"#I>;
def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
// Y register
def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
// Ancillary state registers (implementation defined)

6
llvm/test/MC/Sparc/sparc-special-registers.s
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@ -39,3 +39,9 @@
! CHECK: wr %i0, 7, %asr6 ! encoding: [0x8d,0x86,0x20,0x07]
wr %i0, 7, %fprs
! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
ld [%g2 + 20],%fsr
! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
ld [%g2 + %i5],%fsr

10
llvm/test/MC/Sparc/sparcv9-instructions.s
View File

@ -90,3 +90,13 @@
! V9: stq %f48, [%l0] ! encoding: [0xe3,0x34,0x00,0x00]
stqa %f48, [%l0] 0xf0
stq %f48, [%l0]
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: ldx [%g2 + 20],%fsr
! V9: ldx [%g2+20], %fsr ! encoding: [0xc3,0x08,0xa0,0x14]
ldx [%g2 + 20],%fsr
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: ldx [%g2 + %i5],%fsr
! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d]
ldx [%g2 + %i5],%fsr