From e5485c651efa2b1ab7aded75c3c6a7912d934092 Mon Sep 17 00:00:00 2001 From: Douglas Katzman Date: Wed, 19 Aug 2015 18:34:48 +0000 Subject: [PATCH] [SPARC] Enable writing to floating-point-state register. llvm-svn: 245475 --- .../Target/Sparc/AsmParser/SparcAsmParser.cpp | 9 +++++++++ llvm/lib/Target/Sparc/SparcInstrInfo.td | 16 ++++++++++++++++ llvm/lib/Target/Sparc/SparcRegisterInfo.td | 2 ++ llvm/test/MC/Sparc/sparc-special-registers.s | 6 ++++++ llvm/test/MC/Sparc/sparcv9-instructions.s | 10 ++++++++++ 5 files changed, 43 insertions(+) diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index c96f49e22408..286a5f545ae5 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -772,6 +772,9 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr &Op, case Sparc::PSR: Op = SparcOperand::CreateToken("%psr", S); break; + case Sparc::FSR: + Op = SparcOperand::CreateToken("%fsr", S); + break; case Sparc::WIM: Op = SparcOperand::CreateToken("%wim", S); break; @@ -898,6 +901,12 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, return true; } + if (name.equals("fsr")) { + RegNo = Sparc::FSR; + RegKind = SparcOperand::rk_Special; + return true; + } + if (name.equals("wim")) { RegNo = Sparc::WIM; RegKind = SparcOperand::rk_Special; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index b39e16796e38..21e9f70e4db6 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -434,6 +434,22 @@ let DecoderMethod = "DecodeLoadQFP" in defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>, Requires<[HasV9, HasHardQuad]>; +let DecoderMethod = "DecodeLoadFP" in + let Defs = [FSR] in { + let rd = 0 in { + def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), + "ld [$addr], %fsr", []>; + def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), + "ld [$addr], %fsr", []>; + } + let rd = 1 in { + def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), + "ldx [$addr], %fsr", []>, Requires<[HasV9]>; + def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), + "ldx [$addr], %fsr", []>, Requires<[HasV9]>; + } + } + // Section B.4 - Store Integer Instructions, p. 95 let DecoderMethod = "DecodeStoreInt" in { defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>; diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.td b/llvm/lib/Target/Sparc/SparcRegisterInfo.td index e5bbe2ebc6a7..982377d76ed8 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td @@ -60,6 +60,8 @@ def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code. foreach I = 0-3 in def FCC#I : SparcCtrlReg; +def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register. + // Y register def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>; // Ancillary state registers (implementation defined) diff --git a/llvm/test/MC/Sparc/sparc-special-registers.s b/llvm/test/MC/Sparc/sparc-special-registers.s index e78ddcc35054..9eaab2ee2f43 100644 --- a/llvm/test/MC/Sparc/sparc-special-registers.s +++ b/llvm/test/MC/Sparc/sparc-special-registers.s @@ -39,3 +39,9 @@ ! CHECK: wr %i0, 7, %asr6 ! encoding: [0x8d,0x86,0x20,0x07] wr %i0, 7, %fprs + + ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14] + ld [%g2 + 20],%fsr + + ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d] + ld [%g2 + %i5],%fsr diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s index b663dae62315..c1bb224d2585 100644 --- a/llvm/test/MC/Sparc/sparcv9-instructions.s +++ b/llvm/test/MC/Sparc/sparcv9-instructions.s @@ -90,3 +90,13 @@ ! V9: stq %f48, [%l0] ! encoding: [0xe3,0x34,0x00,0x00] stqa %f48, [%l0] 0xf0 stq %f48, [%l0] + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: ldx [%g2 + 20],%fsr + ! V9: ldx [%g2+20], %fsr ! encoding: [0xc3,0x08,0xa0,0x14] + ldx [%g2 + 20],%fsr + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: ldx [%g2 + %i5],%fsr + ! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d] + ldx [%g2 + %i5],%fsr