forked from OSchip/llvm-project
ARM CPS mode immediate is 5 bits, not 4.
llvm-svn: 136505
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6f3533fb1d
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llvm/lib/Target/ARM
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@ -1319,13 +1319,13 @@ class CPS<dag iops, string asm_ops>
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}
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let M = 1 in
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def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_15:$mode),
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def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
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"$imod\t$iflags, $mode">;
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let mode = 0, M = 0 in
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def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
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let imod = 0, iflags = 0, M = 1 in
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def CPS1p : CPS<(ins imm0_15:$mode), "\t$mode">;
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def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
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// Preload signals the memory system of possible future data/instruction access.
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// These are for disassembly only.
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