forked from OSchip/llvm-project
[mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt
Differential Revision: http://reviews.llvm.org/D13885 llvm-svn: 254405
This commit is contained in:
Hrvoje Varga
parent
d7dbb66eb8
commit
e51b0e13f3
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@ -796,3 +796,65 @@ class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
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let Inst{15-6} = funct;
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let Inst{5-0} = 0x3c;
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}
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class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> ft;
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bits<5> fs;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = ft;
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let Inst{20-16} = fs;
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let Inst{15} = 0;
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let Inst{14} = fmt;
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let Inst{13-6} = funct;
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let Inst{5-0} = 0b111011;
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}
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class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = fs;
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let Inst{20-16} = fd;
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let Inst{15-11} = 0;
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let Inst{10-9} = fmt;
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let Inst{8-0} = 0b000100000;
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}
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class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> ft;
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = ft;
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let Inst{20-16} = fs;
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let Inst{15-11} = fd;
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let Inst{10-9} = fmt;
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let Inst{8-0} = funct;
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}
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class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = fs;
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let Inst{20-16} = fd;
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let Inst{15-11} = 0b00000;
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let Inst{10-9} = fmt;
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let Inst{8-0} = funct;
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}
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@ -132,6 +132,26 @@ class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
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class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
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class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
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class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
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class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
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class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
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class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
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class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
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class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
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0b11001100>;
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class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
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0b11001100>;
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class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
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0b11101100>;
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class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
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0b11101100>;
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class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
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class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
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class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
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class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
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class SELENZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.s", 0, 0b001111000>;
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class SELENZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.d", 1, 0b001111000>;
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class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
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class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
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class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
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class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
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@ -724,6 +744,33 @@ class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
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FGR32Opnd, II_TRUNC>;
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class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
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AFGR64Opnd, II_TRUNC>;
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class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
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FGR32Opnd, II_ROUND>;
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class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
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II_ROUND>;
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class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
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FGR32Opnd, II_ROUND>;
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class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
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FGR64Opnd, II_ROUND>;
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class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
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FGR32Opnd, II_ROUND>;
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class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
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FGR64Opnd, II_ROUND>;
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class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
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class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
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// We must insert a SUBREG_TO_REG around $fd_in
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bit usesCustomInserter = 1;
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}
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class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
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class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
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class SELENZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
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class SELENZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
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class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
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class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
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class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
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class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
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class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
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: Store<opstr, RO>, MMR6Arch<opstr> {
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@ -1121,6 +1168,34 @@ def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
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def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
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def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
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def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
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def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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}
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//===----------------------------------------------------------------------===//
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@ -43,7 +43,7 @@ def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
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BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
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def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
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ROUND_W_FM_MM<0, 0x24>;
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def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
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def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
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ROUND_W_FM_MM<0, 0xec>;
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def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
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@ -52,7 +52,7 @@ def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ROUND_W_FM_MM<1, 0x24>;
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def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
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ROUND_W_FM_MM<1, 0x2c>;
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def ROUND_W_MM : MMRel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
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def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, II_ROUND>,
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ROUND_W_FM_MM<1, 0xec>;
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def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
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ROUND_W_FM_MM<1, 0xac>;
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@ -687,8 +687,10 @@ def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
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def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
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def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
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def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
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def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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let AdditionalPredicates = [NotInMicroMips] in {
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def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
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def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
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defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
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@ -707,14 +709,14 @@ def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
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def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
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@ -728,21 +730,27 @@ def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
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def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
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def NAL; // BAL with rd=0
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def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
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def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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let AdditionalPredicates = [NotInMicroMips] in {
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def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
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}
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def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
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def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
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def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
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def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ multiclass ABSS_M<string opstr, InstrItinClass Itin,
|
|||
|
||||
multiclass ROUND_M<string opstr, InstrItinClass Itin> {
|
||||
def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
|
||||
def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
|
||||
def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
}
|
||||
|
|
@ -267,31 +267,29 @@ defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
|
|||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
|
||||
def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
|
||||
ABSS_FM<0xc, 16>, ISA_MIPS2;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
|
||||
def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
|
||||
ABSS_FM<0xd, 16>, ISA_MIPS2;
|
||||
def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
|
||||
ABSS_FM<0xe, 16>, ISA_MIPS2;
|
||||
def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
|
||||
ABSS_FM<0xf, 16>, ISA_MIPS2;
|
||||
}
|
||||
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
|
||||
ABSS_FM<0x24, 16>;
|
||||
|
||||
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
|
||||
defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
|
||||
defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
|
||||
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
|
||||
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
|
||||
|
||||
let DecoderNamespace = "Mips64" in {
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
|
||||
ABSS_FM<0x8, 16>, FGR_64;
|
||||
def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
|
||||
ABSS_FM<0x8, 17>, FGR_64;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
|
||||
ABSS_FM<0x9, 16>, FGR_64;
|
||||
def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
|
||||
|
|
|
|||
|
|
@ -237,3 +237,19 @@
|
|||
0xea 0x11 # CHECK: sw16 $4, 4($17)
|
||||
0xe8 0x11 # CHECK: sw16 $zero, 4($17)
|
||||
0x45 0x2a # CHECK: swm16 $16, $17, $ra, 8($sp)
|
||||
0x54 0x44 0x12 0x3b # CHECK: recip.s $f2, $f4
|
||||
0x54 0x44 0x52 0x3b # CHECK: recip.d $f2, $f4
|
||||
0x54 0x82 0x00 0x20 # CHECK: rint.s $f2, $f4
|
||||
0x54 0x82 0x02 0x20 # CHECK: rint.d $f2, $f4
|
||||
0x54 0x44 0x33 0x3b # CHECK: round.l.s $f2, $f4
|
||||
0x54 0x44 0x73 0x3b # CHECK: round.l.d $f2, $f4
|
||||
0x54 0x44 0x3b 0x3b # CHECK: round.w.s $f2, $f4
|
||||
0x54 0x44 0x7b 0x3b # CHECK: round.w.d $f2, $f4
|
||||
0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
|
||||
0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
|
||||
0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
|
||||
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
|
||||
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
|
||||
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
|
||||
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
|
||||
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
|
||||
|
|
|
|||
|
|
@ -150,3 +150,19 @@
|
|||
0xea 0x11 # CHECK: sw16 $4, 4($17)
|
||||
0xe8 0x11 # CHECK: sw16 $zero, 4($17)
|
||||
0x45 0x2a # CHECK: swm16 $16, $17, $ra, 8($sp)
|
||||
0x54 0x44 0x12 0x3b # CHECK: recip.s $f2, $f4
|
||||
0x54 0x44 0x52 0x3b # CHECK: recip.d $f2, $f4
|
||||
0x54 0x82 0x00 0x20 # CHECK: rint.s $f2, $f4
|
||||
0x54 0x82 0x02 0x20 # CHECK: rint.d $f2, $f4
|
||||
0x54 0x44 0x33 0x3b # CHECK: round.l.s $f2, $f4
|
||||
0x54 0x44 0x73 0x3b # CHECK: round.l.d $f2, $f4
|
||||
0x54 0x44 0x3b 0x3b # CHECK: round.w.s $f2, $f4
|
||||
0x54 0x44 0x7b 0x3b # CHECK: round.w.d $f2, $f4
|
||||
0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
|
||||
0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
|
||||
0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
|
||||
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
|
||||
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
|
||||
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
|
||||
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
|
||||
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
|
||||
|
|
|
|||
|
|
@ -230,3 +230,19 @@
|
|||
lbu $4, 8($5) # CHECK: lbu $4, 8($5) # encoding: [0x14,0x85,0x00,0x08]
|
||||
lbe $4, 8($5) # CHECK: lbe $4, 8($5) # encoding: [0x60,0x85,0x68,0x08]
|
||||
lbue $4, 8($5) # CHECK: lbue $4, 8($5) # encoding: [0x60,0x85,0x60,0x08]
|
||||
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
|
||||
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
|
||||
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x54,0x82,0x00,0x20]
|
||||
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x20]
|
||||
round.l.s $f2, $f4 # CHECK: round.l.s $f2, $f4 # encoding: [0x54,0x44,0x33,0x3b]
|
||||
round.l.d $f2, $f4 # CHECK: round.l.d $f2, $f4 # encoding: [0x54,0x44,0x73,0x3b]
|
||||
round.w.s $f2, $f4 # CHECK: round.w.s $f2, $f4 # encoding: [0x54,0x44,0x3b,0x3b]
|
||||
round.w.d $f2, $f4 # CHECK: round.w.d $f2, $f4 # encoding: [0x54,0x44,0x7b,0x3b]
|
||||
sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
|
||||
sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
|
||||
seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
|
||||
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
|
||||
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
|
||||
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
|
||||
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
|
||||
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
|
||||
|
|
|
|||
|
|
@ -130,5 +130,21 @@ a:
|
|||
sw16 $0, 4($17) # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
|
||||
swm $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
|
||||
swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
|
||||
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
|
||||
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
|
||||
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x54,0x82,0x00,0x20]
|
||||
rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x20]
|
||||
round.l.s $f2, $f4 # CHECK: round.l.s $f2, $f4 # encoding: [0x54,0x44,0x33,0x3b]
|
||||
round.l.d $f2, $f4 # CHECK: round.l.d $f2, $f4 # encoding: [0x54,0x44,0x73,0x3b]
|
||||
round.w.s $f2, $f4 # CHECK: round.w.s $f2, $f4 # encoding: [0x54,0x44,0x3b,0x3b]
|
||||
round.w.d $f2, $f4 # CHECK: round.w.d $f2, $f4 # encoding: [0x54,0x44,0x7b,0x3b]
|
||||
sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
|
||||
sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
|
||||
seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
|
||||
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
|
||||
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
|
||||
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
|
||||
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
|
||||
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
|
||||
|
||||
1:
|
||||
|
|
|
|||
Loading…
Reference in New Issue