[Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

llvm-svn: 309230
This commit is contained in:
Eugene Zelenko 2017-07-26 23:20:35 +00:00
parent 08e38d6b3d
commit e4fc6ee790
14 changed files with 237 additions and 179 deletions

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@ -1,4 +1,4 @@
//===--- BitTracker.cpp ---------------------------------------------------===//
//===- BitTracker.cpp -----------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -71,7 +71,7 @@
using namespace llvm;
typedef BitTracker BT;
using BT = BitTracker;
namespace {
@ -927,7 +927,8 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
++It;
} while (FallsThrough && It != End);
typedef MachineBasicBlock::const_succ_iterator succ_iterator;
using succ_iterator = MachineBasicBlock::const_succ_iterator;
if (!DefaultToAll) {
// Need to add all CFG successors that lead to EH landing pads.
// There won't be explicit branches to these blocks, but they must
@ -958,7 +959,8 @@ void BT::visitUsesOf(unsigned Reg) {
if (Trace)
dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
typedef MachineRegisterInfo::use_nodbg_iterator use_iterator;
using use_iterator = MachineRegisterInfo::use_nodbg_iterator;
use_iterator End = MRI.use_nodbg_end();
for (use_iterator I = MRI.use_nodbg_begin(Reg); I != End; ++I) {
MachineInstr *UseI = I->getParent();
@ -1039,7 +1041,8 @@ void BT::run() {
reset();
assert(FlowQ.empty());
typedef GraphTraits<const MachineFunction*> MachineFlowGraphTraits;
using MachineFlowGraphTraits = GraphTraits<const MachineFunction*>;
const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);
unsigned MaxBN = 0;

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@ -1,4 +1,4 @@
//===--- BitTracker.h -------------------------------------------*- C++ -*-===//
//===- BitTracker.h ---------------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -13,7 +13,6 @@
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineOperand.h"
#include <cassert>
#include <cstdint>
@ -27,8 +26,11 @@ namespace llvm {
class ConstantInt;
class MachineRegisterInfo;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class raw_ostream;
class TargetRegisterClass;
class TargetRegisterInfo;
struct BitTracker {
struct BitRef;
@ -38,9 +40,8 @@ struct BitTracker {
struct RegisterCell;
struct MachineEvaluator;
typedef SetVector<const MachineBasicBlock *> BranchTargetList;
typedef std::map<unsigned, RegisterCell> CellMapType;
using BranchTargetList = SetVector<const MachineBasicBlock *>;
using CellMapType = std::map<unsigned, RegisterCell>;
BitTracker(const MachineEvaluator &E, MachineFunction &F);
~BitTracker();
@ -64,10 +65,10 @@ private:
void visitUsesOf(unsigned Reg);
void reset();
typedef std::pair<int,int> CFGEdge;
typedef std::set<CFGEdge> EdgeSetType;
typedef std::set<const MachineInstr *> InstrSetType;
typedef std::queue<CFGEdge> EdgeQueueType;
using CFGEdge = std::pair<int, int>;
using EdgeSetType = std::set<CFGEdge>;
using InstrSetType = std::set<const MachineInstr *>;
using EdgeQueueType = std::queue<CFGEdge>;
EdgeSetType EdgeExec; // Executable flow graph edges.
InstrSetType InstrExec; // Executable instructions.
@ -301,7 +302,7 @@ private:
// The DefaultBitN is here only to avoid frequent reallocation of the
// memory in the vector.
static const unsigned DefaultBitN = 32;
typedef SmallVector<BitValue, DefaultBitN> BitValueList;
using BitValueList = SmallVector<BitValue, DefaultBitN>;
BitValueList Bits;
friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);

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@ -1,4 +1,4 @@
//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
//
// The LLVM Compiler Infrastructure
//
@ -24,6 +24,7 @@
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
@ -35,7 +36,7 @@
using namespace llvm;
using namespace Hexagon;
typedef MCDisassembler::DecodeStatus DecodeStatus;
using DecodeStatus = MCDisassembler::DecodeStatus;
namespace {
@ -60,37 +61,38 @@ public:
void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const;
};
namespace {
uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI,
int64_t Value) {
MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(
MCB, HexagonMCInstrInfo::bundleSize(MCB));
if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
return Value;
unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
int64_t Bits;
bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits);
assert(Success); (void)Success;
uint32_t Upper26 = static_cast<uint32_t>(Bits);
uint32_t Operand = Upper26 | Lower6;
return Operand;
}
HexagonDisassembler const &disassembler(void const *Decoder) {
return *static_cast<HexagonDisassembler const *>(Decoder);
}
template <size_t T>
void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
HexagonDisassembler const &Disassembler = disassembler(Decoder);
int64_t FullValue =
fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI,
SignExtend64<T>(tmp));
int64_t Extended = SignExtend64<32>(FullValue);
HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
}
}
} // end anonymous namespace
static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI,
int64_t Value) {
MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(
MCB, HexagonMCInstrInfo::bundleSize(MCB));
if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
return Value;
unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
int64_t Bits;
bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits);
assert(Success); (void)Success;
uint32_t Upper26 = static_cast<uint32_t>(Bits);
uint32_t Operand = Upper26 | Lower6;
return Operand;
}
static HexagonDisassembler const &disassembler(void const *Decoder) {
return *static_cast<HexagonDisassembler const *>(Decoder);
}
template <size_t T>
static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
HexagonDisassembler const &Disassembler = disassembler(Decoder);
int64_t FullValue =
fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI,
SignExtend64<T>(tmp));
int64_t Extended = SignExtend64<32>(FullValue);
HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
}
// Forward declare these because the auto-generated code will reference them.
// Definitions are further down.
@ -198,8 +200,7 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
return MCDisassembler::Success;
}
namespace {
void adjustDuplex(MCInst &MI, MCContext &Context) {
static void adjustDuplex(MCInst &MI, MCContext &Context) {
switch (MI.getOpcode()) {
case Hexagon::SA1_setin1:
MI.insert(MI.begin() + 1,
@ -213,7 +214,6 @@ void adjustDuplex(MCInst &MI, MCContext &Context) {
break;
}
}
}
DecodeStatus HexagonDisassembler::getSingleInstruction(
MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
@ -551,6 +551,7 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
using namespace Hexagon;
static const MCPhysReg CtrlRegDecoderTable[] = {
/* 0 */ SA0, LC0, SA1, LC1,
/* 4 */ P3_0, C5, M0, M1,
@ -578,6 +579,7 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
using namespace Hexagon;
static const MCPhysReg CtrlReg64DecoderTable[] = {
/* 0 */ C1_0, 0, C3_2, 0,
/* 4 */ C5_4, 0, C7_6, 0,
@ -655,5 +657,3 @@ static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
return MCDisassembler::Success;
}

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@ -1,4 +1,4 @@
//===--- HexagonBitSimplify.cpp -------------------------------------------===//
//===- HexagonBitSimplify.cpp ---------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,10 +7,14 @@
//
//===----------------------------------------------------------------------===//
#include "BitTracker.h"
#include "HexagonBitTracker.h"
#include "HexagonTargetMachine.h"
#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
@ -22,13 +26,13 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
@ -52,10 +56,10 @@ static cl::opt<bool> GenBitSplit("hexbit-bitsplit", cl::Hidden,
cl::init(true), cl::desc("Generate bitsplit instructions"));
static cl::opt<unsigned> MaxExtract("hexbit-max-extract", cl::Hidden,
cl::init(UINT_MAX));
cl::init(std::numeric_limits<unsigned>::max()));
static unsigned CountExtract = 0;
static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden,
cl::init(UINT_MAX));
cl::init(std::numeric_limits<unsigned>::max()));
static unsigned CountBitSplit = 0;
namespace llvm {
@ -180,7 +184,7 @@ namespace {
public:
static char ID;
HexagonBitSimplify() : MachineFunctionPass(ID), MDT(nullptr) {
HexagonBitSimplify() : MachineFunctionPass(ID) {
initializeHexagonBitSimplifyPass(*PassRegistry::getPassRegistry());
}
@ -227,15 +231,14 @@ namespace {
const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
private:
MachineDominatorTree *MDT;
MachineDominatorTree *MDT = nullptr;
bool visitBlock(MachineBasicBlock &B, Transformation &T, RegisterSet &AVs);
static bool hasTiedUse(unsigned Reg, MachineRegisterInfo &MRI,
unsigned NewSub = Hexagon::NoSubRegister);
};
char HexagonBitSimplify::ID = 0;
typedef HexagonBitSimplify HBS;
using HBS = HexagonBitSimplify;
// The purpose of this class is to provide a common facility to traverse
// the function top-down or bottom-up via the dominator tree, and keep
@ -252,6 +255,8 @@ namespace {
} // end anonymous namespace
char HexagonBitSimplify::ID = 0;
INITIALIZE_PASS_BEGIN(HexagonBitSimplify, "hexbit",
"Hexagon bit simplification", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
@ -2767,31 +2772,32 @@ namespace {
public:
static char ID;
HexagonLoopRescheduling() : MachineFunctionPass(ID),
HII(nullptr), HRI(nullptr), MRI(nullptr), BTP(nullptr) {
HexagonLoopRescheduling() : MachineFunctionPass(ID) {
initializeHexagonLoopReschedulingPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
private:
const HexagonInstrInfo *HII;
const HexagonRegisterInfo *HRI;
MachineRegisterInfo *MRI;
BitTracker *BTP;
const HexagonInstrInfo *HII = nullptr;
const HexagonRegisterInfo *HRI = nullptr;
MachineRegisterInfo *MRI = nullptr;
BitTracker *BTP = nullptr;
struct LoopCand {
LoopCand(MachineBasicBlock *lb, MachineBasicBlock *pb,
MachineBasicBlock *eb) : LB(lb), PB(pb), EB(eb) {}
MachineBasicBlock *LB, *PB, *EB;
};
typedef std::vector<MachineInstr*> InstrList;
using InstrList = std::vector<MachineInstr *>;
struct InstrGroup {
BitTracker::RegisterRef Inp, Out;
InstrList Ins;
};
struct PhiInfo {
PhiInfo(MachineInstr &P, MachineBasicBlock &B);
unsigned DefR;
BitTracker::RegisterRef LR, PR; // Loop Register, Preheader Register
MachineBasicBlock *LB, *PB; // Loop Block, Preheader Block
@ -3079,7 +3085,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
// to the beginning of the loop, that input register would need to be
// the loop-carried register (through a phi node) instead of the (currently
// loop-carried) output register.
typedef std::vector<InstrGroup> InstrGroupList;
using InstrGroupList = std::vector<InstrGroup>;
InstrGroupList Groups;
for (unsigned i = 0, n = ShufIns.size(); i < n; ++i) {

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@ -1,4 +1,4 @@
//===--- HexagonBitTracker.cpp --------------------------------------------===//
//===- HexagonBitTracker.cpp ----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -11,7 +11,7 @@
#include "Hexagon.h"
#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonTargetMachine.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
@ -20,6 +20,7 @@
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
@ -34,7 +35,7 @@
using namespace llvm;
typedef BitTracker BT;
using BT = BitTracker;
HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
MachineRegisterInfo &mri,
@ -59,7 +60,9 @@ HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
// passed via registers.
unsigned InVirtReg, InPhysReg = 0;
const Function &F = *MF.getFunction();
typedef Function::const_arg_iterator arg_iterator;
using arg_iterator = Function::const_arg_iterator;
for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
const Argument &Arg = *I;
Type *ATy = Arg.getType();
@ -1212,7 +1215,8 @@ unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
}
unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
typedef MachineRegisterInfo::livein_iterator iterator;
using iterator = MachineRegisterInfo::livein_iterator;
for (iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) {
if (I->first == PReg)
return I->second;

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@ -1,4 +1,4 @@
//===--- HexagonBitTracker.h ------------------------------------*- C++ -*-===//
//===- HexagonBitTracker.h --------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -18,12 +18,16 @@ namespace llvm {
class HexagonInstrInfo;
class HexagonRegisterInfo;
class MachineFrameInfo;
class MachineFunction;
class MachineInstr;
class MachineRegisterInfo;
struct HexagonEvaluator : public BitTracker::MachineEvaluator {
typedef BitTracker::CellMapType CellMapType;
typedef BitTracker::RegisterRef RegisterRef;
typedef BitTracker::RegisterCell RegisterCell;
typedef BitTracker::BranchTargetList BranchTargetList;
using CellMapType = BitTracker::CellMapType;
using RegisterRef = BitTracker::RegisterRef;
using RegisterCell = BitTracker::RegisterCell;
using BranchTargetList = BitTracker::BranchTargetList;
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
const HexagonInstrInfo &tii, MachineFunction &mf);
@ -59,7 +63,7 @@ private:
uint16_t Width = 0;
};
// Map VR -> extension type.
typedef DenseMap<unsigned, ExtType> RegExtMap;
using RegExtMap = DenseMap<unsigned, ExtType>;
RegExtMap VRX;
};

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@ -1,4 +1,4 @@
//===--- HexagonBlockRanges.cpp -------------------------------------------===//
//===- HexagonBlockRanges.cpp ---------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -24,8 +24,10 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <map>
#include <utility>
using namespace llvm;

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@ -1,4 +1,4 @@
//===--- HexagonBlockRanges.h -----------------------------------*- C++ -*-===//
//===- HexagonBlockRanges.h -------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -10,7 +10,6 @@
#define HEXAGON_BLOCK_RANGES_H
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include <cassert>
#include <map>
#include <set>
@ -23,6 +22,7 @@ class HexagonSubtarget;
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class MachineRegisterInfo;
class raw_ostream;
class TargetInstrInfo;
class TargetRegisterInfo;
@ -32,11 +32,12 @@ struct HexagonBlockRanges {
struct RegisterRef {
unsigned Reg, Sub;
bool operator<(RegisterRef R) const {
return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
}
};
typedef std::set<RegisterRef> RegisterSet;
using RegisterSet = std::set<RegisterRef>;
// This is to represent an "index", which is an abstraction of a position
// of an instruction within a basic block.
@ -49,7 +50,7 @@ struct HexagonBlockRanges {
First = 11 // 10th + 1st
};
IndexType() : Index(None) {}
IndexType() = default;
IndexType(unsigned Idx) : Index(Idx) {}
static bool isInstr(IndexType X) { return X.Index >= First; }
@ -68,13 +69,13 @@ struct HexagonBlockRanges {
bool operator> (IndexType Idx) const;
bool operator>= (IndexType Idx) const;
unsigned Index;
unsigned Index = None;
};
// A range of indices, essentially a representation of a live range.
// This is also used to represent "dead ranges", i.e. ranges where a
// register is dead.
class IndexRange : public std::pair<IndexType,IndexType> {
class IndexRange : public std::pair<IndexType, IndexType> {
public:
IndexRange() = default;
IndexRange(IndexType Start, IndexType End, bool F = false, bool T = false)
@ -138,7 +139,8 @@ struct HexagonBlockRanges {
std::map<IndexType,MachineInstr*> Map;
};
typedef std::map<RegisterRef,RangeList> RegToRangeMap;
using RegToRangeMap = std::map<RegisterRef, RangeList>;
RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap);
RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap);
static RegisterSet expandToSubRegs(RegisterRef R,

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@ -1,4 +1,4 @@
//===--- HexagonCommonGEP.cpp ---------------------------------------------===//
//===- HexagonCommonGEP.cpp -----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -11,6 +11,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/LoopInfo.h"
@ -27,7 +28,6 @@
#include "llvm/IR/Use.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/IR/Verifier.h"
#include "llvm/Pass.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Casting.h"
@ -66,12 +66,12 @@ namespace llvm {
namespace {
struct GepNode;
typedef std::set<GepNode*> NodeSet;
typedef std::map<GepNode*,Value*> NodeToValueMap;
typedef std::vector<GepNode*> NodeVect;
typedef std::map<GepNode*,NodeVect> NodeChildrenMap;
typedef std::set<Use*> UseSet;
typedef std::map<GepNode*,UseSet> NodeToUsesMap;
using NodeSet = std::set<GepNode *>;
using NodeToValueMap = std::map<GepNode *, Value *>;
using NodeVect = std::vector<GepNode *>;
using NodeChildrenMap = std::map<GepNode *, NodeVect>;
using UseSet = std::set<Use *>;
using NodeToUsesMap = std::map<GepNode *, UseSet>;
// Numbering map for gep nodes. Used to keep track of ordering for
// gep nodes.
@ -114,9 +114,9 @@ namespace {
}
private:
typedef std::map<Value*,GepNode*> ValueToNodeMap;
typedef std::vector<Value*> ValueVect;
typedef std::map<GepNode*,ValueVect> NodeToValuesMap;
using ValueToNodeMap = std::map<Value *, GepNode *>;
using ValueVect = std::vector<Value *>;
using NodeToValuesMap = std::map<GepNode *, ValueVect>;
void getBlockTraversalOrder(BasicBlock *Root, ValueVect &Order);
bool isHandledGepForm(GetElementPtrInst *GepI);
@ -160,6 +160,7 @@ namespace {
} // end anonymous namespace
char HexagonCommonGEP::ID = 0;
INITIALIZE_PASS_BEGIN(HexagonCommonGEP, "hcommgep", "Hexagon Common GEP",
false, false)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
@ -179,15 +180,15 @@ namespace {
InBounds = 0x08
};
uint32_t Flags;
uint32_t Flags = 0;
union {
GepNode *Parent;
Value *BaseVal;
};
Value *Idx;
Type *PTy; // Type of the pointer operand.
Value *Idx = nullptr;
Type *PTy = nullptr; // Type of the pointer operand.
GepNode() : Flags(0), Parent(nullptr), Idx(nullptr), PTy(nullptr) {}
GepNode() : Parent(nullptr) {}
GepNode(const GepNode *N) : Flags(N->Flags), Idx(N->Idx), PTy(N->PTy) {
if (Flags & Root)
BaseVal = N->BaseVal;
@ -267,7 +268,8 @@ namespace {
template <typename NodeContainer>
void dump_node_container(raw_ostream &OS, const NodeContainer &S) {
typedef typename NodeContainer::const_iterator const_iterator;
using const_iterator = typename NodeContainer::const_iterator;
for (const_iterator I = S.begin(), E = S.end(); I != E; ++I)
OS << *I << ' ' << **I << '\n';
}
@ -282,7 +284,8 @@ namespace {
raw_ostream &operator<< (raw_ostream &OS,
const NodeToUsesMap &M) LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<< (raw_ostream &OS, const NodeToUsesMap &M){
typedef NodeToUsesMap::const_iterator const_iterator;
using const_iterator = NodeToUsesMap::const_iterator;
for (const_iterator I = M.begin(), E = M.end(); I != E; ++I) {
const UseSet &Us = I->second;
OS << I->first << " -> #" << Us.size() << '{';
@ -300,6 +303,7 @@ namespace {
struct in_set {
in_set(const NodeSet &S) : NS(S) {}
bool operator() (GepNode *N) const {
return NS.find(N) != NS.end();
}
@ -426,7 +430,8 @@ void HexagonCommonGEP::collect() {
static void invert_find_roots(const NodeVect &Nodes, NodeChildrenMap &NCM,
NodeVect &Roots) {
typedef NodeVect::const_iterator const_iterator;
using const_iterator = NodeVect::const_iterator;
for (const_iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
GepNode *N = *I;
if (N->Flags & GepNode::Root) {
@ -458,9 +463,9 @@ static void nodes_for_root(GepNode *Root, NodeChildrenMap &NCM,
namespace {
typedef std::set<NodeSet> NodeSymRel;
typedef std::pair<GepNode*,GepNode*> NodePair;
typedef std::set<NodePair> NodePairSet;
using NodeSymRel = std::set<NodeSet>;
using NodePair = std::pair<GepNode *, GepNode *>;
using NodePairSet = std::set<NodePair>;
} // end anonymous namespace
@ -529,7 +534,7 @@ void HexagonCommonGEP::common() {
// To do this we need to compare all pairs of nodes. To save time,
// first, partition the set of all nodes into sets of potentially equal
// nodes, and then compare pairs from within each partition.
typedef std::map<unsigned,NodeSet> NodeSetMap;
using NodeSetMap = std::map<unsigned, NodeSet>;
NodeSetMap MaybeEq;
for (NodeVect::iterator I = Nodes.begin(), E = Nodes.end(); I != E; ++I) {
@ -588,7 +593,7 @@ void HexagonCommonGEP::common() {
});
// Create a projection from a NodeSet to the minimal element in it.
typedef std::map<const NodeSet*,GepNode*> ProjMap;
using ProjMap = std::map<const NodeSet *, GepNode *>;
ProjMap PM;
for (NodeSymRel::iterator I = EqRel.begin(), E = EqRel.end(); I != E; ++I) {
const NodeSet &S = *I;
@ -717,7 +722,9 @@ static BasicBlock *nearest_common_dominatee(DominatorTree *DT, T &Blocks) {
template <typename T>
static BasicBlock::iterator first_use_of_in_block(T &Values, BasicBlock *B) {
BasicBlock::iterator FirstUse = B->end(), BEnd = B->end();
typedef typename T::iterator iterator;
using iterator = typename T::iterator;
for (iterator I = Values.begin(), E = Values.end(); I != E; ++I) {
Value *V = *I;
// If V is used in a PHI node, the use belongs to the incoming block,
@ -1247,7 +1254,9 @@ void HexagonCommonGEP::removeDeadCode() {
for (unsigned i = BO.size(); i > 0; --i) {
BasicBlock *B = cast<BasicBlock>(BO[i-1]);
BasicBlock::InstListType &IL = B->getInstList();
typedef BasicBlock::InstListType::reverse_iterator reverse_iterator;
using reverse_iterator = BasicBlock::InstListType::reverse_iterator;
ValueVect Ins;
for (reverse_iterator I = IL.rbegin(), E = IL.rend(); I != E; ++I)
Ins.push_back(&*I);

View File

@ -1,4 +1,4 @@
//===--- HexagonConstPropagation.cpp --------------------------------------===//
//===- HexagonConstPropagation.cpp ----------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -26,13 +26,16 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Type.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <cstring>
@ -224,7 +227,8 @@ namespace {
void print(raw_ostream &os, const TargetRegisterInfo &TRI) const;
private:
typedef std::map<unsigned,LatticeCell> MapType;
using MapType = std::map<unsigned, LatticeCell>;
MapType Map;
// To avoid creating "top" entries, return a const reference to
// this cell in "get". Also, have a "Bottom" cell to return from
@ -232,7 +236,8 @@ namespace {
LatticeCell Top, Bottom;
public:
typedef MapType::const_iterator const_iterator;
using const_iterator = MapType::const_iterator;
const_iterator begin() const { return Map.begin(); }
const_iterator end() const { return Map.end(); }
};
@ -254,10 +259,10 @@ namespace {
MachineRegisterInfo *MRI;
MachineConstEvaluator &MCE;
typedef std::pair<unsigned,unsigned> CFGEdge;
typedef std::set<CFGEdge> SetOfCFGEdge;
typedef std::set<const MachineInstr*> SetOfInstr;
typedef std::queue<CFGEdge> QueueOfCFGEdge;
using CFGEdge = std::pair<unsigned, unsigned>;
using SetOfCFGEdge = std::set<CFGEdge>;
using SetOfInstr = std::set<const MachineInstr *>;
using QueueOfCFGEdge = std::queue<CFGEdge>;
LatticeCell Bottom;
CellMap Cells;
@ -291,7 +296,7 @@ namespace {
// - A function "rewrite", that given the cell map after propagation,
// could rewrite instruction MI in a more beneficial form. Return
// "true" if a change has been made, "false" otherwise.
typedef MachineConstPropagator::CellMap CellMap;
using CellMap = MachineConstPropagator::CellMap;
virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs) = 0;
virtual bool evaluate(const Register &R, const LatticeCell &SrcC,
@ -1028,7 +1033,7 @@ bool MachineConstPropagator::rewrite(MachineFunction &MF) {
// This is the constant propagation algorithm as described by Wegman-Zadeck.
// Most of the terminology comes from there.
bool MachineConstPropagator::run(MachineFunction &MF) {
DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", 0));
DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", nullptr));
MRI = &MF.getRegInfo();
@ -1043,7 +1048,7 @@ bool MachineConstPropagator::run(MachineFunction &MF) {
DEBUG({
dbgs() << "End of MachineConstPropagator (Changed=" << Changed << ")\n";
if (Changed)
MF.print(dbgs(), 0);
MF.print(dbgs(), nullptr);
});
return Changed;
}
@ -1278,7 +1283,8 @@ bool MachineConstEvaluator::evaluateCMPpi(uint32_t Cmp, uint32_t Props,
bool MachineConstEvaluator::evaluateCMPpp(uint32_t Cmp, uint32_t Props1,
uint32_t Props2, bool &Result) {
typedef ConstantProperties P;
using P = ConstantProperties;
if ((Props1 & P::NaN) && (Props2 & P::NaN))
return false;
if (!(Props1 & P::Finite) || !(Props2 & P::Finite))
@ -1886,10 +1892,10 @@ namespace {
}
};
char HexagonConstPropagation::ID = 0;
} // end anonymous namespace
char HexagonConstPropagation::ID = 0;
INITIALIZE_PASS(HexagonConstPropagation, "hcp", "Hexagon Constant Propagation",
false, false)
@ -2192,7 +2198,8 @@ bool HexagonConstEvaluator::evaluate(const Register &R,
if (Input.isBottom())
return false;
typedef ConstantProperties P;
using P = ConstantProperties;
if (Input.isProperty()) {
uint32_t Ps = Input.properties();
if (Ps & (P::Zero|P::NaN)) {
@ -2837,7 +2844,8 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
if (!L.isSingle()) {
// If this a zero/non-zero cell, we can fold a definition
// of a predicate register.
typedef ConstantProperties P;
using P = ConstantProperties;
uint64_t Ps = L.properties();
if (!(Ps & (P::Zero|P::NonZero)))
continue;
@ -3039,7 +3047,9 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
LatticeCell LS1, LS2;
unsigned CopyOf = 0;
typedef ConstantProperties P;
using P = ConstantProperties;
if (getCell(R1, Inputs, LS1) && (LS1.properties() & P::Zero))
CopyOf = 2;
else if (getCell(R2, Inputs, LS2) && (LS2.properties() & P::Zero))

View File

@ -1,4 +1,4 @@
//===--- HexagonEarlyIfConv.cpp -------------------------------------------===//
//===- HexagonEarlyIfConv.cpp ---------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -99,17 +99,18 @@ namespace llvm {
} // end namespace llvm
namespace {
static cl::opt<bool> EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden,
cl::init(false), cl::desc("Enable branch probability info"));
static cl::opt<unsigned> SizeLimit("eif-limit", cl::init(6), cl::Hidden,
cl::desc("Size limit in Hexagon early if-conversion"));
static cl::opt<bool> SkipExitBranches("eif-no-loop-exit", cl::init(false),
cl::Hidden, cl::desc("Do not convert branches that may exit the loop"));
cl::opt<bool> EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden,
cl::init(false), cl::desc("Enable branch probability info"));
cl::opt<unsigned> SizeLimit("eif-limit", cl::init(6), cl::Hidden,
cl::desc("Size limit in Hexagon early if-conversion"));
cl::opt<bool> SkipExitBranches("eif-no-loop-exit", cl::init(false),
cl::Hidden, cl::desc("Do not convert branches that may exit the loop"));
namespace {
struct PrintMB {
PrintMB(const MachineBasicBlock *B) : MB(B) {}
const MachineBasicBlock *MB;
};
raw_ostream &operator<< (raw_ostream &OS, const PrintMB &P) {
@ -154,9 +155,7 @@ namespace {
public:
static char ID;
HexagonEarlyIfConversion() : MachineFunctionPass(ID),
HII(nullptr), TRI(nullptr), MFN(nullptr), MRI(nullptr), MDT(nullptr),
MLI(nullptr) {
HexagonEarlyIfConversion() : MachineFunctionPass(ID) {
initializeHexagonEarlyIfConversionPass(*PassRegistry::getPassRegistry());
}
@ -175,7 +174,7 @@ namespace {
bool runOnMachineFunction(MachineFunction &MF) override;
private:
typedef DenseSet<MachineBasicBlock*> BlockSetType;
using BlockSetType = DenseSet<MachineBasicBlock *>;
bool isPreheader(const MachineBasicBlock *B) const;
bool matchFlowPattern(MachineBasicBlock *B, MachineLoop *L,
@ -214,20 +213,20 @@ namespace {
void mergeBlocks(MachineBasicBlock *PredB, MachineBasicBlock *SuccB);
void simplifyFlowGraph(const FlowPattern &FP);
const HexagonInstrInfo *HII;
const TargetRegisterInfo *TRI;
MachineFunction *MFN;
MachineRegisterInfo *MRI;
MachineDominatorTree *MDT;
MachineLoopInfo *MLI;
const HexagonInstrInfo *HII = nullptr;
const TargetRegisterInfo *TRI = nullptr;
MachineFunction *MFN = nullptr;
MachineRegisterInfo *MRI = nullptr;
MachineDominatorTree *MDT = nullptr;
MachineLoopInfo *MLI = nullptr;
BlockSetType Deleted;
const MachineBranchProbabilityInfo *MBPI;
};
char HexagonEarlyIfConversion::ID = 0;
} // end anonymous namespace
char HexagonEarlyIfConversion::ID = 0;
INITIALIZE_PASS(HexagonEarlyIfConversion, "hexagon-eif",
"Hexagon early if conversion", false, false)
@ -593,7 +592,9 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B,
// Visit all dominated blocks from the same loop first, then process B.
MachineDomTreeNode *N = MDT->getNode(B);
typedef GraphTraits<MachineDomTreeNode*> GTN;
using GTN = GraphTraits<MachineDomTreeNode *>;
// We will change CFG/DT during this traversal, so take precautions to
// avoid problems related to invalidated iterators. In fact, processing
// a child C of B cannot cause another child to be removed, but it can
@ -601,7 +602,7 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B,
// was removed. This new child C, however, would have been processed
// prior to processing B, so there is no need to process it again.
// Simply keep a list of children of B, and traverse that list.
typedef SmallVector<MachineDomTreeNode*,4> DTNodeVectType;
using DTNodeVectType = SmallVector<MachineDomTreeNode *, 4>;
DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
MachineBasicBlock *SB = (*I)->getBlock();
@ -947,8 +948,10 @@ void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) {
MachineDomTreeNode *IDN = N->getIDom();
if (IDN) {
MachineBasicBlock *IDB = IDN->getBlock();
typedef GraphTraits<MachineDomTreeNode*> GTN;
typedef SmallVector<MachineDomTreeNode*,4> DTNodeVectType;
using GTN = GraphTraits<MachineDomTreeNode *>;
using DTNodeVectType = SmallVector<MachineDomTreeNode *, 4>;
DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
MachineBasicBlock *SB = (*I)->getBlock();

View File

@ -1,4 +1,4 @@
//===--- HexagonExpandCondsets.cpp ----------------------------------------===//
//===- HexagonExpandCondsets.cpp ------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -103,12 +103,15 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <set>
@ -136,10 +139,7 @@ namespace {
public:
static char ID;
HexagonExpandCondsets() :
MachineFunctionPass(ID), HII(nullptr), TRI(nullptr), MRI(nullptr),
LIS(nullptr), CoaLimitActive(false),
TfrLimitActive(false), CoaCounter(0), TfrCounter(0) {
HexagonExpandCondsets() : MachineFunctionPass(ID) {
if (OptCoaLimit.getPosition())
CoaLimitActive = true, CoaLimit = OptCoaLimit;
if (OptTfrLimit.getPosition())
@ -161,14 +161,17 @@ namespace {
bool runOnMachineFunction(MachineFunction &MF) override;
private:
const HexagonInstrInfo *HII;
const TargetRegisterInfo *TRI;
const HexagonInstrInfo *HII = nullptr;
const TargetRegisterInfo *TRI = nullptr;
MachineDominatorTree *MDT;
MachineRegisterInfo *MRI;
LiveIntervals *LIS;
bool CoaLimitActive, TfrLimitActive;
unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter;
MachineRegisterInfo *MRI = nullptr;
LiveIntervals *LIS = nullptr;
bool CoaLimitActive = false;
bool TfrLimitActive = false;
unsigned CoaLimit;
unsigned TfrLimit;
unsigned CoaCounter = 0;
unsigned TfrCounter = 0;
struct RegisterRef {
RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
@ -186,9 +189,10 @@ namespace {
unsigned Reg, Sub;
};
typedef DenseMap<unsigned,unsigned> ReferenceMap;
using ReferenceMap = DenseMap<unsigned, unsigned>;
enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
enum { Exec_Then = 0x10, Exec_Else = 0x20 };
unsigned getMaskForSub(unsigned Sub);
bool isCondset(const MachineInstr &MI);
LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
@ -495,7 +499,6 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
for (RegisterRef R : ImpUses)
MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
}
}
void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
@ -1133,7 +1136,7 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
MRI->replaceRegWith(R2.Reg, R1.Reg);
// Move all live segments from L2 to L1.
typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap;
using ValueInfoMap = DenseMap<VNInfo *, VNInfo *>;
ValueInfoMap VM;
for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
VNInfo *NewVN, *OldVN = I->valno;

View File

@ -1,4 +1,4 @@
//===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
//===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -38,6 +38,7 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCDwarf.h"
@ -45,11 +46,13 @@
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
@ -57,7 +60,6 @@
#include <iterator>
#include <limits>
#include <map>
#include <new>
#include <utility>
#include <vector>
@ -406,9 +408,10 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
MachinePostDominatorTree MPT;
MPT.runOnMachineFunction(MF);
typedef DenseMap<unsigned,unsigned> UnsignedMap;
using UnsignedMap = DenseMap<unsigned, unsigned>;
using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;
UnsignedMap RPO;
typedef ReversePostOrderTraversal<const MachineFunction*> RPOTType;
RPOTType RPOT(&MF);
unsigned RPON = 0;
for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
@ -1452,7 +1455,8 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
// object for it.
CSI.clear();
typedef TargetFrameLowering::SpillSlot SpillSlot;
using SpillSlot = TargetFrameLowering::SpillSlot;
unsigned NumFixed;
int MinOffset = 0; // CS offsets are negative.
const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
@ -2019,11 +2023,11 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
auto &MRI = MF.getRegInfo();
HexagonBlockRanges HBR(MF);
typedef std::map<MachineBasicBlock*,HexagonBlockRanges::InstrIndexMap>
BlockIndexMap;
typedef std::map<MachineBasicBlock*,HexagonBlockRanges::RangeList>
BlockRangeMap;
typedef HexagonBlockRanges::IndexType IndexType;
using BlockIndexMap =
std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
using BlockRangeMap =
std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
using IndexType = HexagonBlockRanges::IndexType;
struct SlotInfo {
BlockRangeMap Map;

View File

@ -1,4 +1,4 @@
//=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
//==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -20,8 +20,13 @@
namespace llvm {
class BitVector;
class HexagonInstrInfo;
class HexagonRegisterInfo;
class MachineFunction;
class MachineInstr;
class MachineRegisterInfo;
class TargetRegisterClass;
class HexagonFrameLowering : public TargetFrameLowering {
public:
@ -52,11 +57,13 @@ public:
// We always reserve call frame as a part of the initial stack allocation.
return true;
}
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override {
// Override this function to avoid calling hasFP before CSI is set
// (the default implementation calls hasFP).
return true;
}
MachineBasicBlock::iterator
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
@ -97,7 +104,7 @@ public:
void insertCFIInstructions(MachineFunction &MF) const;
private:
typedef std::vector<CalleeSavedInfo> CSIVect;
using CSIVect = std::vector<CalleeSavedInfo>;
void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
unsigned SP, unsigned CF) const;