From e4d63a499d32d631041d6c1bcbd9f6e2309e690c Mon Sep 17 00:00:00 2001 From: Marina Yatsina Date: Mon, 22 Jan 2018 13:24:10 +0000 Subject: [PATCH] Fixing warnings caused by commit 323095 Change-Id: I4e1f81db2f5382a820f4016c23b243e4d5aebf51 llvm-svn: 323114 --- llvm/lib/CodeGen/ExecutionDomainFix.cpp | 4 ++-- llvm/lib/CodeGen/LoopTraversal.cpp | 6 +++--- llvm/lib/CodeGen/ReachingDefAnalysis.cpp | 10 +++++----- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/llvm/lib/CodeGen/ExecutionDomainFix.cpp b/llvm/lib/CodeGen/ExecutionDomainFix.cpp index a32260a986d1..776fc6bb410a 100644 --- a/llvm/lib/CodeGen/ExecutionDomainFix.cpp +++ b/llvm/lib/CodeGen/ExecutionDomainFix.cpp @@ -167,7 +167,7 @@ void ExecutionDomainFix::enterBasicBlock( // Try to coalesce live-out registers from predecessors. for (MachineBasicBlock *pred : MBB->predecessors()) { - assert(pred->getNumber() < MBBOutRegsInfos.size() && + assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() && "Should have pre-allocated MBBInfos for all MBBs"); LiveRegsDVInfo &Incoming = MBBOutRegsInfos[pred->getNumber()]; // Incoming is null if this is a backedge from a BB @@ -208,7 +208,7 @@ void ExecutionDomainFix::enterBasicBlock( void ExecutionDomainFix::leaveBasicBlock( const LoopTraversal::TraversedMBBInfo &TraversedMBB) { assert(!LiveRegs.empty() && "Must enter basic block first."); - int MBBNumber = TraversedMBB.MBB->getNumber(); + unsigned MBBNumber = TraversedMBB.MBB->getNumber(); assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number."); // Save register clearances at end of MBB - used by enterBasicBlock(). diff --git a/llvm/lib/CodeGen/LoopTraversal.cpp b/llvm/lib/CodeGen/LoopTraversal.cpp index 7b7e0ee13bc3..a02d10e09d7d 100644 --- a/llvm/lib/CodeGen/LoopTraversal.cpp +++ b/llvm/lib/CodeGen/LoopTraversal.cpp @@ -14,7 +14,7 @@ using namespace llvm; bool LoopTraversal::isBlockDone(MachineBasicBlock *MBB) { - int MBBNumber = MBB->getNumber(); + unsigned MBBNumber = MBB->getNumber(); assert(MBBNumber < MBBInfos.size() && "Unexpected basic block number."); return MBBInfos[MBBNumber].PrimaryCompleted && MBBInfos[MBBNumber].IncomingCompleted == @@ -33,7 +33,7 @@ LoopTraversal::TraversalOrder LoopTraversal::traverse(MachineFunction &MF) { for (MachineBasicBlock *MBB : RPOT) { // N.B: IncomingProcessed and IncomingCompleted were already updated while // processing this block's predecessors. - int MBBNumber = MBB->getNumber(); + unsigned MBBNumber = MBB->getNumber(); assert(MBBNumber < MBBInfos.size() && "Unexpected basic block number."); MBBInfos[MBBNumber].PrimaryCompleted = true; MBBInfos[MBBNumber].PrimaryIncoming = MBBInfos[MBBNumber].IncomingProcessed; @@ -45,7 +45,7 @@ LoopTraversal::TraversalOrder LoopTraversal::traverse(MachineFunction &MF) { bool Done = isBlockDone(ActiveMBB); MBBTraversalOrder.push_back(TraversedMBBInfo(ActiveMBB, Primary, Done)); for (MachineBasicBlock *Succ : ActiveMBB->successors()) { - int SuccNumber = Succ->getNumber(); + unsigned SuccNumber = Succ->getNumber(); assert(SuccNumber < MBBInfos.size() && "Unexpected basic block number."); if (!isBlockDone(Succ)) { diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp index d24803a21861..6b131b250be7 100644 --- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -23,7 +23,7 @@ void ReachingDefAnalysis::enterBasicBlock( const LoopTraversal::TraversedMBBInfo &TraversedMBB) { MachineBasicBlock *MBB = TraversedMBB.MBB; - int MBBNumber = MBB->getNumber(); + unsigned MBBNumber = MBB->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number."); MBBReachingDefs[MBBNumber].resize(NumRegUnits); @@ -53,7 +53,7 @@ void ReachingDefAnalysis::enterBasicBlock( // Try to coalesce live-out registers from predecessors. for (MachineBasicBlock *pred : MBB->predecessors()) { - assert(pred->getNumber() < MBBOutRegsInfos.size() && + assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() && "Should have pre-allocated MBBInfos for all MBBs"); const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()]; // Incoming is null if this is a backedge from a BB @@ -77,7 +77,7 @@ void ReachingDefAnalysis::enterBasicBlock( void ReachingDefAnalysis::leaveBasicBlock( const LoopTraversal::TraversedMBBInfo &TraversedMBB) { assert(!LiveRegs.empty() && "Must enter basic block first."); - int MBBNumber = TraversedMBB.MBB->getNumber(); + unsigned MBBNumber = TraversedMBB.MBB->getNumber(); assert(MBBNumber < MBBOutRegsInfos.size() && "Unexpected basic block number."); // Save register clearances at end of MBB - used by enterBasicBlock(). @@ -95,7 +95,7 @@ void ReachingDefAnalysis::leaveBasicBlock( void ReachingDefAnalysis::processDefs(MachineInstr *MI) { assert(!MI->isDebugValue() && "Won't process debug values"); - int MBBNumber = MI->getParent()->getNumber(); + unsigned MBBNumber = MI->getParent()->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number."); const MCInstrDesc &MCID = MI->getDesc(); @@ -174,7 +174,7 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) { assert(InstIds.count(MI) && "Unexpected machine instuction."); int InstId = InstIds[MI]; int DefRes = ReachingDedDefaultVal; - int MBBNumber = MI->getParent()->getNumber(); + unsigned MBBNumber = MI->getParent()->getNumber(); assert(MBBNumber < MBBReachingDefs.size() && "Unexpected basic block number."); int LatestDef = ReachingDedDefaultVal;