forked from OSchip/llvm-project
[MIPS GlobalISel] Select MSA vector generic and builtin add
Select vector G_ADD for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_addv_<format> will be transformed into G_ADD in legalizeIntrinsic and selected in the same way. __builtin_msa_addvi_<format> will be directly selected into ADDVI_<format> in legalizeIntrinsic. MIR tests for it have unnecessary additional copies. Capture current state of tests with run-pass=legalizer with a test in test/CodeGen/MIR/Mips. Differential Revision: https://reviews.llvm.org/D68984 llvm-svn: 375501
This commit is contained in:
Petar Avramovic
parent
e5dd30f77e
commit
e4af9de36c
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@ -41,6 +41,14 @@ CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
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return false;
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}
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static bool CheckTyN(unsigned N, const LegalityQuery &Query,
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std::initializer_list<LLT> SupportedValues) {
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for (auto &Val : SupportedValues)
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if (Val == Query.Types[N])
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return true;
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return false;
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}
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MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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using namespace TargetOpcode;
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@ -53,10 +61,20 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT p0 = LLT::pointer(0, 32);
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getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
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getActionDefinitionsBuilder({G_SUB, G_MUL})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_ADD)
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTyN(0, Query, {s32}))
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return true;
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if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
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return true;
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return false;
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})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
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.lowerFor({{s32, s1}});
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@ -270,6 +288,33 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
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return true;
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}
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static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
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MachineIRBuilder &MIRBuilder,
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const MipsSubtarget &ST) {
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assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
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if (!MIRBuilder.buildInstr(Opcode)
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.add(MI.getOperand(0))
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.add(MI.getOperand(2))
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.add(MI.getOperand(3))
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.constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
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*ST.getRegBankInfo()))
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return false;
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MI.eraseFromParent();
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return true;
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}
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static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
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MachineIRBuilder &MIRBuilder,
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const MipsSubtarget &ST) {
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assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
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MIRBuilder.buildInstr(Opcode)
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.add(MI.getOperand(0))
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.add(MI.getOperand(2))
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.add(MI.getOperand(3));
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MI.eraseFromParent();
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return true;
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}
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bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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@ -306,6 +351,19 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MI.eraseFromParent();
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return true;
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}
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case Intrinsic::mips_addv_b:
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case Intrinsic::mips_addv_h:
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case Intrinsic::mips_addv_w:
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case Intrinsic::mips_addv_d:
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return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
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case Intrinsic::mips_addvi_b:
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return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
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case Intrinsic::mips_addvi_h:
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return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
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case Intrinsic::mips_addvi_w:
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return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
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case Intrinsic::mips_addvi_d:
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return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
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default:
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break;
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}
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@ -437,7 +437,6 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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switch (Opc) {
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case G_TRUNC:
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case G_ADD:
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case G_SUB:
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case G_MUL:
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case G_UMULH:
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@ -460,6 +459,11 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case G_VASTART:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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break;
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case G_ADD:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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if (Op0Size == 128)
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OperandsMapping = getMSAMapping(MF);
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break;
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case G_STORE:
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case G_LOAD:
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if (Op0Size == 128) {
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@ -0,0 +1,27 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -stop-after=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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; Check there are no COPY instructions surrounding ADDVI_W instruction.
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; All virtual registers were created with createGenericVirtualRegister
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; which sets RegClassOrRegBank in VRegInfo.
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; Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
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; gets selected into ADDVI_W works as expected.
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; Check that setRegClassOrRegBank.mir has same output.
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declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
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define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
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; P5600-LABEL: name: add_v4i32_builtin_imm
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; P5600: bb.1.entry:
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; P5600: liveins: $a0, $a1
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
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; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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entry:
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%0 = load <4 x i32>, <4 x i32>* %a, align 16
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%1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
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store <4 x i32> %1, <4 x i32>* %c, align 16
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ret void
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}
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@ -0,0 +1,41 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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# Check there are COPY instructions surrounding ADDVI_W instruction.
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# MIParser does not set RegClassOrRegBank for parsed virtual registers.
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# Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
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# gets selected into ADDVI_W creates additional copies.
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# FixMe: Make sure this test has same output as setRegClassOrRegBank.ll.
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--- |
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declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
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define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
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...
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---
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name: add_v4i32_builtin_imm
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; P5600-LABEL: name: add_v4i32_builtin_imm
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; P5600: liveins: $a0, $a1
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
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; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
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; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
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; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:_(p0) = COPY $a0
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%1:_(p0) = COPY $a1
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%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
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G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
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RetRA
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...
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@ -0,0 +1,130 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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--- |
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define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
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define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
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define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
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define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
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...
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---
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name: add_v16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: add_v16i8
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]]
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; P5600: ST_B [[ADDV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<16 x s8>) = G_ADD %4, %3
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G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: add_v8i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: add_v8i16
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[ADDV_H:%[0-9]+]]:msa128h = ADDV_H [[LD_H1]], [[LD_H]]
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; P5600: ST_H [[ADDV_H]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<8 x s16>) = G_ADD %4, %3
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G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: add_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: add_v4i32
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[ADDV_W:%[0-9]+]]:msa128w = ADDV_W [[LD_W1]], [[LD_W]]
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; P5600: ST_W [[ADDV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<4 x s32>) = G_ADD %4, %3
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G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: add_v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: add_v2i64
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[ADDV_D:%[0-9]+]]:msa128d = ADDV_D [[LD_D1]], [[LD_D]]
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; P5600: ST_D [[ADDV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<2 x s64>) = G_ADD %4, %3
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G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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@ -0,0 +1,122 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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--- |
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define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
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define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
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define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
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define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
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...
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---
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name: add_v16i8
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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||||
|
||||
; P5600-LABEL: name: add_v16i8
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<16 x s8>) = G_ADD %4, %3
|
||||
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v8i16
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v8i16
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<8 x s16>) = G_ADD %4, %3
|
||||
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v4i32
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v4i32
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<4 x s32>) = G_ADD %4, %3
|
||||
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v2i64
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v2i64
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<2 x s64>) = G_ADD %4, %3
|
||||
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
|
||||
--- |
|
||||
|
||||
declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)
|
||||
define void @add_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
|
||||
|
||||
declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)
|
||||
define void @add_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
|
||||
|
||||
declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)
|
||||
define void @add_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
|
||||
|
||||
declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)
|
||||
define void @add_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
|
||||
|
||||
declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)
|
||||
define void @add_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) { entry: ret void }
|
||||
|
||||
declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)
|
||||
define void @add_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) { entry: ret void }
|
||||
|
||||
declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
|
||||
define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
|
||||
|
||||
declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)
|
||||
define void @add_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) { entry: ret void }
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v16i8_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v16i8_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addv.b), %3(<16 x s8>), %4(<16 x s8>)
|
||||
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v8i16_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v8i16_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addv.h), %3(<8 x s16>), %4(<8 x s16>)
|
||||
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v4i32_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v4i32_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addv.w), %3(<4 x s32>), %4(<4 x s32>)
|
||||
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v2i64_builtin
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v2i64_builtin
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD]], [[LOAD1]]
|
||||
; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addv.d), %3(<2 x s64>), %4(<2 x s64>)
|
||||
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v16i8_builtin_imm
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; P5600-LABEL: name: add_v16i8_builtin_imm
|
||||
; P5600: liveins: $a0, $a1
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[COPY2:%[0-9]+]]:msa128b = COPY [[LOAD]](<16 x s8>)
|
||||
; P5600: [[ADDVI_B:%[0-9]+]]:msa128b = ADDVI_B [[COPY2]], 3
|
||||
; P5600: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ADDVI_B]]
|
||||
; P5600: G_STORE [[COPY3]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%3:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.b), %2(<16 x s8>), 3
|
||||
G_STORE %3(<16 x s8>), %1(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v8i16_builtin_imm
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; P5600-LABEL: name: add_v8i16_builtin_imm
|
||||
; P5600: liveins: $a0, $a1
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[COPY2:%[0-9]+]]:msa128h = COPY [[LOAD]](<8 x s16>)
|
||||
; P5600: [[ADDVI_H:%[0-9]+]]:msa128h = ADDVI_H [[COPY2]], 18
|
||||
; P5600: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ADDVI_H]]
|
||||
; P5600: G_STORE [[COPY3]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%3:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.h), %2(<8 x s16>), 18
|
||||
G_STORE %3(<8 x s16>), %1(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v4i32_builtin_imm
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; P5600-LABEL: name: add_v4i32_builtin_imm
|
||||
; P5600: liveins: $a0, $a1
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>)
|
||||
; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25
|
||||
; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]]
|
||||
; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25
|
||||
G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v2i64_builtin_imm
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; P5600-LABEL: name: add_v2i64_builtin_imm
|
||||
; P5600: liveins: $a0, $a1
|
||||
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
|
||||
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[COPY2:%[0-9]+]]:msa128d = COPY [[LOAD]](<2 x s64>)
|
||||
; P5600: [[ADDVI_D:%[0-9]+]]:msa128d = ADDVI_D [[COPY2]], 31
|
||||
; P5600: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ADDVI_D]]
|
||||
; P5600: G_STORE [[COPY3]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.d), %2(<2 x s64>), 31
|
||||
G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
|
||||
|
||||
define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
|
||||
; P5600-LABEL: add_v16i8:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.b $w0, 0($4)
|
||||
; P5600-NEXT: ld.b $w1, 0($5)
|
||||
; P5600-NEXT: addv.b $w0, $w1, $w0
|
||||
; P5600-NEXT: st.b $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %a, align 16
|
||||
%1 = load <16 x i8>, <16 x i8>* %b, align 16
|
||||
%add = add <16 x i8> %1, %0
|
||||
store <16 x i8> %add, <16 x i8>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
|
||||
; P5600-LABEL: add_v8i16:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.h $w0, 0($4)
|
||||
; P5600-NEXT: ld.h $w1, 0($5)
|
||||
; P5600-NEXT: addv.h $w0, $w1, $w0
|
||||
; P5600-NEXT: st.h $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* %a, align 16
|
||||
%1 = load <8 x i16>, <8 x i16>* %b, align 16
|
||||
%add = add <8 x i16> %1, %0
|
||||
store <8 x i16> %add, <8 x i16>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
|
||||
; P5600-LABEL: add_v4i32:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.w $w0, 0($4)
|
||||
; P5600-NEXT: ld.w $w1, 0($5)
|
||||
; P5600-NEXT: addv.w $w0, $w1, $w0
|
||||
; P5600-NEXT: st.w $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = load <4 x i32>, <4 x i32>* %b, align 16
|
||||
%add = add <4 x i32> %1, %0
|
||||
store <4 x i32> %add, <4 x i32>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
|
||||
; P5600-LABEL: add_v2i64:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.d $w0, 0($4)
|
||||
; P5600-NEXT: ld.d $w1, 0($5)
|
||||
; P5600-NEXT: addv.d $w0, $w1, $w0
|
||||
; P5600-NEXT: st.d $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%add = add <2 x i64> %1, %0
|
||||
store <2 x i64> %add, <2 x i64>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
|
||||
|
||||
declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)
|
||||
define void @add_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
|
||||
; P5600-LABEL: add_v16i8_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.b $w0, 0($4)
|
||||
; P5600-NEXT: ld.b $w1, 0($5)
|
||||
; P5600-NEXT: addv.b $w0, $w0, $w1
|
||||
; P5600-NEXT: st.b $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %a, align 16
|
||||
%1 = load <16 x i8>, <16 x i8>* %b, align 16
|
||||
%2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
|
||||
store <16 x i8> %2, <16 x i8>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)
|
||||
define void @add_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
|
||||
; P5600-LABEL: add_v8i16_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.h $w0, 0($4)
|
||||
; P5600-NEXT: ld.h $w1, 0($5)
|
||||
; P5600-NEXT: addv.h $w0, $w0, $w1
|
||||
; P5600-NEXT: st.h $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* %a, align 16
|
||||
%1 = load <8 x i16>, <8 x i16>* %b, align 16
|
||||
%2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
|
||||
store <8 x i16> %2, <8 x i16>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)
|
||||
define void @add_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
|
||||
; P5600-LABEL: add_v4i32_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.w $w0, 0($4)
|
||||
; P5600-NEXT: ld.w $w1, 0($5)
|
||||
; P5600-NEXT: addv.w $w0, $w0, $w1
|
||||
; P5600-NEXT: st.w $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = load <4 x i32>, <4 x i32>* %b, align 16
|
||||
%2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
|
||||
store <4 x i32> %2, <4 x i32>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)
|
||||
define void @add_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
|
||||
; P5600-LABEL: add_v2i64_builtin:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.d $w0, 0($4)
|
||||
; P5600-NEXT: ld.d $w1, 0($5)
|
||||
; P5600-NEXT: addv.d $w0, $w0, $w1
|
||||
; P5600-NEXT: st.d $w0, 0($6)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = load <2 x i64>, <2 x i64>* %b, align 16
|
||||
%2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
|
||||
store <2 x i64> %2, <2 x i64>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)
|
||||
define void @add_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) {
|
||||
; P5600-LABEL: add_v16i8_builtin_imm:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.b $w0, 0($4)
|
||||
; P5600-NEXT: addvi.b $w0, $w0, 3
|
||||
; P5600-NEXT: st.b $w0, 0($5)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %a, align 16
|
||||
%1 = tail call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %0, i32 3)
|
||||
store <16 x i8> %1, <16 x i8>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)
|
||||
define void @add_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) {
|
||||
; P5600-LABEL: add_v8i16_builtin_imm:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.h $w0, 0($4)
|
||||
; P5600-NEXT: addvi.h $w0, $w0, 18
|
||||
; P5600-NEXT: st.h $w0, 0($5)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <8 x i16>, <8 x i16>* %a, align 16
|
||||
%1 = tail call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %0, i32 18)
|
||||
store <8 x i16> %1, <8 x i16>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
|
||||
define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
|
||||
; P5600-LABEL: add_v4i32_builtin_imm:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.w $w0, 0($4)
|
||||
; P5600-NEXT: addvi.w $w0, $w0, 25
|
||||
; P5600-NEXT: st.w $w0, 0($5)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* %a, align 16
|
||||
%1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
|
||||
store <4 x i32> %1, <4 x i32>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)
|
||||
define void @add_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) {
|
||||
; P5600-LABEL: add_v2i64_builtin_imm:
|
||||
; P5600: # %bb.0: # %entry
|
||||
; P5600-NEXT: ld.d $w0, 0($4)
|
||||
; P5600-NEXT: addvi.d $w0, $w0, 31
|
||||
; P5600-NEXT: st.d $w0, 0($5)
|
||||
; P5600-NEXT: jr $ra
|
||||
; P5600-NEXT: nop
|
||||
entry:
|
||||
%0 = load <2 x i64>, <2 x i64>* %a, align 16
|
||||
%1 = tail call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %0, i32 31)
|
||||
store <2 x i64> %1, <2 x i64>* %c, align 16
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
|
||||
--- |
|
||||
|
||||
define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
|
||||
define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
|
||||
define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
|
||||
define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v16i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v16i8
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:fprb(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<16 x s8>) = G_ADD %4, %3
|
||||
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v8i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v8i16
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:fprb(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<8 x s16>) = G_ADD %4, %3
|
||||
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v4i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v4i32
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:fprb(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<4 x s32>) = G_ADD %4, %3
|
||||
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
---
|
||||
name: add_v2i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
; P5600-LABEL: name: add_v2i64
|
||||
; P5600: liveins: $a0, $a1, $a2
|
||||
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
|
||||
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
|
||||
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
|
||||
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
|
||||
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
|
||||
; P5600: [[ADD:%[0-9]+]]:fprb(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
|
||||
; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
|
||||
; P5600: RetRA
|
||||
%0:_(p0) = COPY $a0
|
||||
%1:_(p0) = COPY $a1
|
||||
%2:_(p0) = COPY $a2
|
||||
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
|
||||
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
|
||||
%5:_(<2 x s64>) = G_ADD %4, %3
|
||||
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
|
||||
RetRA
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue