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Thumb2 prefer ADD register encoding T2 to T3 when possible. 

rdar://10529664

llvm-svn: 145860
This commit is contained in:
Jim Grosbach 2011-12-05 22:16:39 +00:00
parent 1a10f29b2f
commit e489babf9b
1 changed files with 20 additions and 0 deletions
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20
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -5238,6 +5238,26 @@ processInstruction(MCInst &Inst,
return true;
}
break;
case ARM::t2ADDrr: {
// If the destination and first source operand are the same, and
// there's no setting of the flags, use encoding T2 instead of T3.
// Note that this is only for ADD, not SUB. This mirrors the system
// 'as' behaviour. Make sure the wide encoding wasn't explicit.
if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
Inst.getOperand(5).getReg() != 0 ||
(static_cast<ARMOperand*>(Operands[2])->isToken() &&
static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
break;
MCInst TmpInst;
TmpInst.setOpcode(ARM::tADDhirr);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
case ARM::tB:
// A Thumb conditional branch outside of an IT block is a tBcc.
if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {