forked from OSchip/llvm-project
[AMDGPU] gfx11 ds instructions
MC layer support for ds instructions Contributors: Piotr Sobczak <Piotr.Sobczak@amd.com> Patch 14/N for upstreaming of AMDGPU gfx11 architecture. Depends on D126463 Reviewed By: arsenm, #amdgpu Differential Revision: https://reviews.llvm.org/D126468
This commit is contained in:
Joe Nash
parent
dc5175adef
commit
e4870c8357
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@ -52,8 +52,8 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
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let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
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}
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class DS_Real <DS_Pseudo ps> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
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InstSI <ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands>,
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Enc64 {
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let isPseudo = 0;
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@ -72,6 +72,9 @@ class DS_Real <DS_Pseudo ps> :
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let IsAtomicRet = ps.IsAtomicRet;
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let IsAtomicNoRet = ps.IsAtomicNoRet;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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// encoding fields
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bits<10> vdst;
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bits<1> gds;
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@ -172,6 +175,22 @@ multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
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}
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}
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class DS_0A1D_RET_GDS<string opName, RegisterClass rc = VGPR_32, RegisterClass src = rc,
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RegisterOperand dst_op = getLdStRegisterOperand<rc>.ret,
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RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
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: DS_Pseudo<opName,
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(outs dst_op:$vdst),
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(ins src_op:$data0, offset:$offset),
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" $vdst, $data0$offset gds"> {
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let has_addr = 0;
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let has_data1 = 0;
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let has_gds = 0;
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let gdsValue = 1;
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let AsmMatchConverter = "cvtDSGds";
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let hasSideEffects = 1;
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}
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class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
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RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
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: DS_Pseudo<opName,
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@ -469,6 +488,15 @@ let SubtargetPredicate = isGFX940Plus in {
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defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc_gfx9<"ds_pk_add_rtn_bf16", VGPR_32, "ds_pk_add_bf16">;
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} // End SubtargetPredicate = isGFX940Plus
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defm DS_CMPSTORE_B32 : DS_1A2D_NORET_mc<"ds_cmpstore_b32">;
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defm DS_CMPSTORE_F32 : DS_1A2D_NORET_mc<"ds_cmpstore_f32">;
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defm DS_CMPSTORE_B64 : DS_1A2D_NORET_mc<"ds_cmpstore_b64", VReg_64>;
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defm DS_CMPSTORE_F64 : DS_1A2D_NORET_mc<"ds_cmpstore_f64", VReg_64>;
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defm DS_CMPSTORE_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b32", VGPR_32, "ds_cmpstore_b32">;
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defm DS_CMPSTORE_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f32", VGPR_32, "ds_cmpstore_f32">;
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defm DS_CMPSTORE_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_b64", VReg_64, "ds_cmpstore_b64">;
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defm DS_CMPSTORE_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpstore_rtn_f64", VReg_64, "ds_cmpstore_f64">;
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defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">;
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defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
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defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
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@ -676,6 +704,18 @@ let SubtargetPredicate = HasLDSFPAtomicAdd, OtherPredicates = [HasDsSrc2Insts] i
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def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definitions for GFX11 and newer.
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//===----------------------------------------------------------------------===//
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let SubtargetPredicate = isGFX11Plus in {
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def DS_ADD_GS_REG_RTN : DS_0A1D_RET_GDS<"ds_add_gs_reg_rtn", VReg_64, VGPR_32>;
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def DS_SUB_GS_REG_RTN : DS_0A1D_RET_GDS<"ds_sub_gs_reg_rtn", VReg_64, VGPR_32>;
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} // let SubtargetPredicate = isGFX11Plus
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//===----------------------------------------------------------------------===//
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// DS Patterns
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//===----------------------------------------------------------------------===//
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@ -952,6 +992,7 @@ multiclass DSAtomicRetNoRetPat_mc<DS_Pseudo inst, DS_Pseudo noRetInst,
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let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
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// Caution, the order of src and cmp is the *opposite* of the BUFFER_ATOMIC_CMPSWAP opcode.
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class DSAtomicCmpXChgSwapped<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
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(frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
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@ -975,8 +1016,26 @@ multiclass DSAtomicCmpXChgSwapped_mc<DS_Pseudo inst, DS_Pseudo noRetInst, ValueT
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def : DSAtomicCmpXChgSwapped<inst, vt, !cast<PatFrag>(frag#"_region_m0_ret_"#vt.Size), 1>;
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def : DSAtomicCmpXChgSwapped<noRetInst, vt, !cast<PatFrag>(frag#"_region_m0_noret_"#vt.Size), 1>;
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}
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} // End SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10
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let SubtargetPredicate = isGFX11Plus in {
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// The order of src and cmp agrees with the BUFFER_ATOMIC_CMPSWAP opcode.
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class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
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(frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
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(inst $ptr, getVregSrcForVT<vt>.ret:$swap, getVregSrcForVT<vt>.ret:$cmp, offset:$offset, (i1 gds))
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>;
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multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, DS_Pseudo noRetInst, ValueType vt, string frag> {
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def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
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!cast<PatFrag>(frag#"_local_ret_"#vt.Size)>;
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def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(noRetInst)#"_gfx9"), vt,
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!cast<PatFrag>(frag#"_local_noret_"#vt.Size)>;
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def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0_ret_"#vt.Size), 1>;
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def : DSAtomicCmpXChg<noRetInst, vt, !cast<PatFrag>(frag#"_region_m0_noret_"#vt.Size), 1>;
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}
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} // End SubtargetPredicate = isGFX11Plus
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// 32-bit atomics.
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defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
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@ -993,7 +1052,14 @@ defm : DSAtomicRetNoRetPat_mc<DS_MIN_RTN_U32, DS_MIN_U32, i32, "atomic_load_umin
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defm : DSAtomicRetNoRetPat_mc<DS_MAX_RTN_U32, DS_MAX_U32, i32, "atomic_load_umax">;
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defm : DSAtomicRetNoRetPat_mc<DS_MIN_RTN_F32, DS_MIN_F32, f32, "atomic_load_fmin">;
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defm : DSAtomicRetNoRetPat_mc<DS_MAX_RTN_F32, DS_MAX_F32, f32, "atomic_load_fmax">;
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let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
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defm : DSAtomicCmpXChgSwapped_mc<DS_CMPST_RTN_B32, DS_CMPST_B32, i32, "atomic_cmp_swap">;
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}
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let SubtargetPredicate = isGFX11Plus in {
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defm : DSAtomicCmpXChg_mc<DS_CMPSTORE_RTN_B32, DS_CMPSTORE_B32, i32, "atomic_cmp_swap">;
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}
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let SubtargetPredicate = HasLDSFPAtomicAdd in {
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defm : DSAtomicRetNoRetPat_mc<DS_ADD_RTN_F32, DS_ADD_F32, f32, "atomic_load_fadd">;
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@ -1015,7 +1081,13 @@ defm : DSAtomicRetNoRetPat_mc<DS_MAX_RTN_U64, DS_MAX_U64, i64, "atomic_load_umax
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defm : DSAtomicRetNoRetPat_mc<DS_MIN_RTN_F64, DS_MIN_F64, f64, "atomic_load_fmin">;
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defm : DSAtomicRetNoRetPat_mc<DS_MAX_RTN_F64, DS_MAX_F64, f64, "atomic_load_fmax">;
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let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
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defm : DSAtomicCmpXChgSwapped_mc<DS_CMPST_RTN_B64, DS_CMPST_B64, i64, "atomic_cmp_swap">;
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} // End SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10
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let SubtargetPredicate = isGFX11Plus in {
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defm : DSAtomicCmpXChg_mc<DS_CMPSTORE_RTN_B64, DS_CMPSTORE_B64, i64, "atomic_cmp_swap">;
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} // End SubtargetPredicate = isGFX11Plus
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let SubtargetPredicate = isGFX90APlus in {
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def : DSAtomicRetPat<DS_ADD_RTN_F64, f64, atomic_load_fadd_local_ret_64>;
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@ -1045,11 +1117,11 @@ def : Pat <
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Base ENC_DS for GFX6, GFX7, GFX10.
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// Base ENC_DS for GFX6, GFX7, GFX10, GFX11.
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//===----------------------------------------------------------------------===//
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class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
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DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
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class Base_DS_Real_gfx6_gfx7_gfx10_gfx11<bits<8> op, DS_Pseudo ps, int ef, string opName = ps.Mnemonic> :
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DS_Real<ps, opName>, SIMCInstr <ps.Mnemonic, ef> {
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let Inst{7-0} = !if(ps.has_offset0, offset0, 0);
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let Inst{15-8} = !if(ps.has_offset1, offset1, 0);
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@ -1062,20 +1134,90 @@ class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
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let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
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}
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//===----------------------------------------------------------------------===//
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// GFX11.
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//===----------------------------------------------------------------------===//
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let AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11" in {
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multiclass DS_Real_gfx11<bits<8> op> {
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def _gfx11 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11<op, !cast<DS_Pseudo>(NAME),
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SIEncodingFamily.GFX11>;
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}
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multiclass DS_Real_Renamed_gfx11<bits<8> op, DS_Pseudo backing_pseudo, string real_name> {
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def _gfx11 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11<op, backing_pseudo, SIEncodingFamily.GFX11, real_name>,
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MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX11Plus]>;
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}
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} // End AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11"
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defm DS_STORE_B32 : DS_Real_Renamed_gfx11<0x00d, DS_WRITE_B32, "ds_store_b32">;
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defm DS_STORE_2ADDR_B32 : DS_Real_Renamed_gfx11<0x00e, DS_WRITE2_B32, "ds_store_2addr_b32">;
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defm DS_STORE_2ADDR_STRIDE64_B32 : DS_Real_Renamed_gfx11<0x00f, DS_WRITE2ST64_B32, "ds_store_2addr_stride64_b32">;
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defm DS_STORE_B8 : DS_Real_Renamed_gfx11<0x01e, DS_WRITE_B8, "ds_store_b8">;
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defm DS_STORE_B16 : DS_Real_Renamed_gfx11<0x01f, DS_WRITE_B16, "ds_store_b16">;
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defm DS_STOREXCHG_RTN_B32 : DS_Real_Renamed_gfx11<0x02d, DS_WRXCHG_RTN_B32, "ds_storexchg_rtn_b32">;
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defm DS_STOREXCHG_2ADDR_RTN_B32 : DS_Real_Renamed_gfx11<0x02e, DS_WRXCHG2_RTN_B32, "ds_storexchg_2addr_rtn_b32">;
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defm DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32 : DS_Real_Renamed_gfx11<0x02f, DS_WRXCHG2ST64_RTN_B32, "ds_storexchg_2addr_stride64_rtn_b32">;
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defm DS_LOAD_B32 : DS_Real_Renamed_gfx11<0x036, DS_READ_B32, "ds_load_b32">;
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defm DS_LOAD_2ADDR_B32 : DS_Real_Renamed_gfx11<0x037, DS_READ2_B32, "ds_load_2addr_b32">;
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defm DS_LOAD_2ADDR_STRIDE64_B32 : DS_Real_Renamed_gfx11<0x038, DS_READ2ST64_B32, "ds_load_2addr_stride64_b32">;
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defm DS_LOAD_I8 : DS_Real_Renamed_gfx11<0x039, DS_READ_I8, "ds_load_i8">;
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defm DS_LOAD_U8 : DS_Real_Renamed_gfx11<0x03a, DS_READ_U8, "ds_load_u8">;
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defm DS_LOAD_I16 : DS_Real_Renamed_gfx11<0x03b, DS_READ_I16, "ds_load_i16">;
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defm DS_LOAD_U16 : DS_Real_Renamed_gfx11<0x03c, DS_READ_U16, "ds_load_u16">;
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defm DS_STORE_B64 : DS_Real_Renamed_gfx11<0x04d, DS_WRITE_B64, "ds_store_b64">;
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defm DS_STORE_2ADDR_B64 : DS_Real_Renamed_gfx11<0x04e, DS_WRITE2_B64, "ds_store_2addr_b64">;
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defm DS_STORE_2ADDR_STRIDE64_B64 : DS_Real_Renamed_gfx11<0x04f, DS_WRITE2ST64_B64, "ds_store_2addr_stride64_b64">;
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defm DS_STOREXCHG_RTN_B64 : DS_Real_Renamed_gfx11<0x06d, DS_WRXCHG_RTN_B64, "ds_storexchg_rtn_b64">;
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defm DS_STOREXCHG_2ADDR_RTN_B64 : DS_Real_Renamed_gfx11<0x06e, DS_WRXCHG2_RTN_B64, "ds_storexchg_2addr_rtn_b64">;
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defm DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64 : DS_Real_Renamed_gfx11<0x06f, DS_WRXCHG2ST64_RTN_B64, "ds_storexchg_2addr_stride64_rtn_b64">;
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defm DS_LOAD_B64 : DS_Real_Renamed_gfx11<0x076, DS_READ_B64, "ds_load_b64">;
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defm DS_LOAD_2ADDR_B64 : DS_Real_Renamed_gfx11<0x077, DS_READ2_B64, "ds_load_2addr_b64">;
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defm DS_LOAD_2ADDR_STRIDE64_B64 : DS_Real_Renamed_gfx11<0x078, DS_READ2ST64_B64, "ds_load_2addr_stride64_b64">;
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defm DS_STORE_B8_D16_HI : DS_Real_Renamed_gfx11<0x0a0, DS_WRITE_B8_D16_HI, "ds_store_b8_d16_hi">;
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defm DS_STORE_B16_D16_HI : DS_Real_Renamed_gfx11<0x0a1, DS_WRITE_B16_D16_HI, "ds_store_b16_d16_hi">;
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defm DS_LOAD_U8_D16 : DS_Real_Renamed_gfx11<0x0a2, DS_READ_U8_D16, "ds_load_u8_d16">;
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defm DS_LOAD_U8_D16_HI : DS_Real_Renamed_gfx11<0x0a3, DS_READ_U8_D16_HI, "ds_load_u8_d16_hi">;
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defm DS_LOAD_I8_D16 : DS_Real_Renamed_gfx11<0x0a4, DS_READ_I8_D16, "ds_load_i8_d16">;
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defm DS_LOAD_I8_D16_HI : DS_Real_Renamed_gfx11<0x0a5, DS_READ_I8_D16_HI, "ds_load_i8_d16_hi">;
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defm DS_LOAD_U16_D16 : DS_Real_Renamed_gfx11<0x0a6, DS_READ_U16_D16, "ds_load_u16_d16">;
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defm DS_LOAD_U16_D16_HI : DS_Real_Renamed_gfx11<0x0a7, DS_READ_U16_D16_HI, "ds_load_u16_d16_hi">;
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defm DS_STORE_ADDTID_B32 : DS_Real_Renamed_gfx11<0x0b0, DS_WRITE_ADDTID_B32, "ds_store_addtid_b32">;
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defm DS_LOAD_ADDTID_B32 : DS_Real_Renamed_gfx11<0x0b1, DS_READ_ADDTID_B32, "ds_load_addtid_b32">;
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defm DS_STORE_B96 : DS_Real_Renamed_gfx11<0x0de, DS_WRITE_B96, "ds_store_b96">;
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defm DS_STORE_B128 : DS_Real_Renamed_gfx11<0x0df, DS_WRITE_B128, "ds_store_b128">;
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defm DS_LOAD_B96 : DS_Real_Renamed_gfx11<0x0fe, DS_READ_B96, "ds_load_b96">;
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defm DS_LOAD_B128 : DS_Real_Renamed_gfx11<0x0ff, DS_READ_B128, "ds_load_b128">;
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// DS_CMPST_* are renamed to DS_CMPSTORE_* in GFX11, but also the data operands (src and cmp) are swapped
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// comparing to pre-GFX11.
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// Note: the mnemonic alias is not generated to avoid a potential ambiguity due to the semantics change.
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defm DS_CMPSTORE_B32 : DS_Real_gfx11<0x010>;
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defm DS_CMPSTORE_F32 : DS_Real_gfx11<0x011>;
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defm DS_CMPSTORE_RTN_B32 : DS_Real_gfx11<0x030>;
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defm DS_CMPSTORE_RTN_F32 : DS_Real_gfx11<0x031>;
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defm DS_CMPSTORE_B64 : DS_Real_gfx11<0x050>;
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defm DS_CMPSTORE_F64 : DS_Real_gfx11<0x051>;
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defm DS_CMPSTORE_RTN_B64 : DS_Real_gfx11<0x070>;
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defm DS_CMPSTORE_RTN_F64 : DS_Real_gfx11<0x071>;
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defm DS_ADD_RTN_F32 : DS_Real_gfx11<0x079>;
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defm DS_ADD_GS_REG_RTN : DS_Real_gfx11<0x07a>;
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defm DS_SUB_GS_REG_RTN : DS_Real_gfx11<0x07b>;
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//===----------------------------------------------------------------------===//
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// GFX10.
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//===----------------------------------------------------------------------===//
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let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
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let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
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multiclass DS_Real_gfx10<bits<8> op> {
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def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
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def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11<op, !cast<DS_Pseudo>(NAME),
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SIEncodingFamily.GFX10>;
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}
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} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
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} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
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|
||||
defm DS_ADD_F32 : DS_Real_gfx10<0x015>;
|
||||
defm DS_ADD_RTN_F32 : DS_Real_gfx10<0x055>;
|
||||
defm DS_ADD_SRC2_F32 : DS_Real_gfx10<0x095>;
|
||||
defm DS_WRITE_B8_D16_HI : DS_Real_gfx10<0x0a0>;
|
||||
defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
|
||||
defm DS_READ_U8_D16 : DS_Real_gfx10<0x0a2>;
|
||||
|
|
@ -1086,95 +1228,118 @@ defm DS_READ_U16_D16 : DS_Real_gfx10<0x0a6>;
|
|||
defm DS_READ_U16_D16_HI : DS_Real_gfx10<0x0a7>;
|
||||
defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
|
||||
defm DS_READ_ADDTID_B32 : DS_Real_gfx10<0x0b1>;
|
||||
defm DS_PERMUTE_B32 : DS_Real_gfx10<0x0b2>;
|
||||
defm DS_BPERMUTE_B32 : DS_Real_gfx10<0x0b3>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GFX7, GFX10.
|
||||
// GFX10, GFX11.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass DS_Real_gfx10_gfx11<bits<8> op> :
|
||||
DS_Real_gfx10<op>, DS_Real_gfx11<op>;
|
||||
|
||||
defm DS_ADD_F32 : DS_Real_gfx10_gfx11<0x015>;
|
||||
defm DS_ADD_SRC2_F32 : DS_Real_gfx10<0x095>;
|
||||
defm DS_PERMUTE_B32 : DS_Real_gfx10_gfx11<0x0b2>;
|
||||
defm DS_BPERMUTE_B32 : DS_Real_gfx10_gfx11<0x0b3>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GFX7, GFX10, GFX11.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
|
||||
multiclass DS_Real_gfx7<bits<8> op> {
|
||||
def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
|
||||
def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11<op, !cast<DS_Pseudo>(NAME),
|
||||
SIEncodingFamily.SI>;
|
||||
}
|
||||
} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
|
||||
|
||||
multiclass DS_Real_gfx7_gfx10_gfx11<bits<8> op> :
|
||||
DS_Real_gfx7<op>, DS_Real_gfx10_gfx11<op>;
|
||||
|
||||
multiclass DS_Real_gfx7_gfx10<bits<8> op> :
|
||||
DS_Real_gfx7<op>, DS_Real_gfx10<op>;
|
||||
|
||||
// FIXME-GFX7: Add tests when upstreaming this part.
|
||||
defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
|
||||
defm DS_WRAP_RTN_B32 : DS_Real_gfx7_gfx10<0x034>;
|
||||
defm DS_CONDXCHG32_RTN_B64 : DS_Real_gfx7_gfx10<0x07e>;
|
||||
defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10_gfx11<0x018>;
|
||||
defm DS_WRAP_RTN_B32 : DS_Real_gfx7_gfx10_gfx11<0x034>;
|
||||
defm DS_CONDXCHG32_RTN_B64 : DS_Real_gfx7_gfx10_gfx11<0x07e>;
|
||||
defm DS_WRITE_B96 : DS_Real_gfx7_gfx10<0x0de>;
|
||||
defm DS_WRITE_B128 : DS_Real_gfx7_gfx10<0x0df>;
|
||||
defm DS_READ_B96 : DS_Real_gfx7_gfx10<0x0fe>;
|
||||
defm DS_READ_B128 : DS_Real_gfx7_gfx10<0x0ff>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GFX6, GFX7, GFX10.
|
||||
// GFX6, GFX7, GFX10, GFX11.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
|
||||
multiclass DS_Real_gfx6_gfx7<bits<8> op> {
|
||||
def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
|
||||
def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11<op, !cast<DS_Pseudo>(NAME),
|
||||
SIEncodingFamily.SI>;
|
||||
}
|
||||
} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
|
||||
|
||||
multiclass DS_Real_gfx6_gfx7_gfx10_gfx11<bits<8> op> :
|
||||
DS_Real_gfx6_gfx7<op>, DS_Real_gfx10_gfx11<op>;
|
||||
|
||||
multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
|
||||
DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
|
||||
|
||||
defm DS_ADD_U32 : DS_Real_gfx6_gfx7_gfx10<0x000>;
|
||||
defm DS_SUB_U32 : DS_Real_gfx6_gfx7_gfx10<0x001>;
|
||||
defm DS_RSUB_U32 : DS_Real_gfx6_gfx7_gfx10<0x002>;
|
||||
defm DS_INC_U32 : DS_Real_gfx6_gfx7_gfx10<0x003>;
|
||||
defm DS_DEC_U32 : DS_Real_gfx6_gfx7_gfx10<0x004>;
|
||||
defm DS_MIN_I32 : DS_Real_gfx6_gfx7_gfx10<0x005>;
|
||||
defm DS_MAX_I32 : DS_Real_gfx6_gfx7_gfx10<0x006>;
|
||||
defm DS_MIN_U32 : DS_Real_gfx6_gfx7_gfx10<0x007>;
|
||||
defm DS_MAX_U32 : DS_Real_gfx6_gfx7_gfx10<0x008>;
|
||||
defm DS_AND_B32 : DS_Real_gfx6_gfx7_gfx10<0x009>;
|
||||
defm DS_OR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00a>;
|
||||
defm DS_XOR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00b>;
|
||||
defm DS_MSKOR_B32 : DS_Real_gfx6_gfx7_gfx10<0x00c>;
|
||||
defm DS_ADD_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x000>;
|
||||
defm DS_SUB_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x001>;
|
||||
defm DS_RSUB_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x002>;
|
||||
defm DS_INC_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x003>;
|
||||
defm DS_DEC_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x004>;
|
||||
defm DS_MIN_I32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x005>;
|
||||
defm DS_MAX_I32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x006>;
|
||||
defm DS_MIN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x007>;
|
||||
defm DS_MAX_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x008>;
|
||||
defm DS_AND_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x009>;
|
||||
defm DS_OR_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x00a>;
|
||||
defm DS_XOR_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x00b>;
|
||||
defm DS_MSKOR_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x00c>;
|
||||
|
||||
defm DS_WRITE_B32 : DS_Real_gfx6_gfx7_gfx10<0x00d>;
|
||||
defm DS_WRITE2_B32 : DS_Real_gfx6_gfx7_gfx10<0x00e>;
|
||||
defm DS_WRITE2ST64_B32 : DS_Real_gfx6_gfx7_gfx10<0x00f>;
|
||||
defm DS_CMPST_B32 : DS_Real_gfx6_gfx7_gfx10<0x010>;
|
||||
defm DS_CMPST_F32 : DS_Real_gfx6_gfx7_gfx10<0x011>;
|
||||
defm DS_MIN_F32 : DS_Real_gfx6_gfx7_gfx10<0x012>;
|
||||
defm DS_MAX_F32 : DS_Real_gfx6_gfx7_gfx10<0x013>;
|
||||
defm DS_NOP : DS_Real_gfx6_gfx7_gfx10<0x014>;
|
||||
defm DS_GWS_INIT : DS_Real_gfx6_gfx7_gfx10<0x019>;
|
||||
defm DS_GWS_SEMA_V : DS_Real_gfx6_gfx7_gfx10<0x01a>;
|
||||
defm DS_GWS_SEMA_BR : DS_Real_gfx6_gfx7_gfx10<0x01b>;
|
||||
defm DS_GWS_SEMA_P : DS_Real_gfx6_gfx7_gfx10<0x01c>;
|
||||
defm DS_GWS_BARRIER : DS_Real_gfx6_gfx7_gfx10<0x01d>;
|
||||
|
||||
defm DS_MIN_F32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x012>;
|
||||
defm DS_MAX_F32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x013>;
|
||||
defm DS_NOP : DS_Real_gfx6_gfx7_gfx10_gfx11<0x014>;
|
||||
defm DS_GWS_INIT : DS_Real_gfx6_gfx7_gfx10_gfx11<0x019>;
|
||||
defm DS_GWS_SEMA_V : DS_Real_gfx6_gfx7_gfx10_gfx11<0x01a>;
|
||||
defm DS_GWS_SEMA_BR : DS_Real_gfx6_gfx7_gfx10_gfx11<0x01b>;
|
||||
defm DS_GWS_SEMA_P : DS_Real_gfx6_gfx7_gfx10_gfx11<0x01c>;
|
||||
defm DS_GWS_BARRIER : DS_Real_gfx6_gfx7_gfx10_gfx11<0x01d>;
|
||||
|
||||
defm DS_WRITE_B8 : DS_Real_gfx6_gfx7_gfx10<0x01e>;
|
||||
defm DS_WRITE_B16 : DS_Real_gfx6_gfx7_gfx10<0x01f>;
|
||||
defm DS_ADD_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x020>;
|
||||
defm DS_SUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x021>;
|
||||
defm DS_RSUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x022>;
|
||||
defm DS_INC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x023>;
|
||||
defm DS_DEC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x024>;
|
||||
defm DS_MIN_RTN_I32 : DS_Real_gfx6_gfx7_gfx10<0x025>;
|
||||
defm DS_MAX_RTN_I32 : DS_Real_gfx6_gfx7_gfx10<0x026>;
|
||||
defm DS_MIN_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x027>;
|
||||
defm DS_MAX_RTN_U32 : DS_Real_gfx6_gfx7_gfx10<0x028>;
|
||||
defm DS_AND_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x029>;
|
||||
defm DS_OR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02a>;
|
||||
defm DS_XOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02b>;
|
||||
defm DS_MSKOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02c>;
|
||||
|
||||
defm DS_ADD_RTN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x020>;
|
||||
defm DS_SUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x021>;
|
||||
defm DS_RSUB_RTN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x022>;
|
||||
defm DS_INC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x023>;
|
||||
defm DS_DEC_RTN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x024>;
|
||||
defm DS_MIN_RTN_I32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x025>;
|
||||
defm DS_MAX_RTN_I32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x026>;
|
||||
defm DS_MIN_RTN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x027>;
|
||||
defm DS_MAX_RTN_U32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x028>;
|
||||
defm DS_AND_RTN_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x029>;
|
||||
defm DS_OR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x02a>;
|
||||
defm DS_XOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x02b>;
|
||||
defm DS_MSKOR_RTN_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x02c>;
|
||||
|
||||
defm DS_WRXCHG_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02d>;
|
||||
defm DS_WRXCHG2_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02e>;
|
||||
defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
|
||||
defm DS_CMPST_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x030>;
|
||||
defm DS_CMPST_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x031>;
|
||||
defm DS_MIN_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x032>;
|
||||
defm DS_MAX_RTN_F32 : DS_Real_gfx6_gfx7_gfx10<0x033>;
|
||||
defm DS_SWIZZLE_B32 : DS_Real_gfx6_gfx7_gfx10<0x035>;
|
||||
|
||||
defm DS_MIN_RTN_F32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x032>;
|
||||
defm DS_MAX_RTN_F32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x033>;
|
||||
defm DS_SWIZZLE_B32 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x035>;
|
||||
|
||||
defm DS_READ_B32 : DS_Real_gfx6_gfx7_gfx10<0x036>;
|
||||
defm DS_READ2_B32 : DS_Real_gfx6_gfx7_gfx10<0x037>;
|
||||
defm DS_READ2ST64_B32 : DS_Real_gfx6_gfx7_gfx10<0x038>;
|
||||
|
|
@ -1182,49 +1347,55 @@ defm DS_READ_I8 : DS_Real_gfx6_gfx7_gfx10<0x039>;
|
|||
defm DS_READ_U8 : DS_Real_gfx6_gfx7_gfx10<0x03a>;
|
||||
defm DS_READ_I16 : DS_Real_gfx6_gfx7_gfx10<0x03b>;
|
||||
defm DS_READ_U16 : DS_Real_gfx6_gfx7_gfx10<0x03c>;
|
||||
defm DS_CONSUME : DS_Real_gfx6_gfx7_gfx10<0x03d>;
|
||||
defm DS_APPEND : DS_Real_gfx6_gfx7_gfx10<0x03e>;
|
||||
defm DS_ORDERED_COUNT : DS_Real_gfx6_gfx7_gfx10<0x03f>;
|
||||
defm DS_ADD_U64 : DS_Real_gfx6_gfx7_gfx10<0x040>;
|
||||
defm DS_SUB_U64 : DS_Real_gfx6_gfx7_gfx10<0x041>;
|
||||
defm DS_RSUB_U64 : DS_Real_gfx6_gfx7_gfx10<0x042>;
|
||||
defm DS_INC_U64 : DS_Real_gfx6_gfx7_gfx10<0x043>;
|
||||
defm DS_DEC_U64 : DS_Real_gfx6_gfx7_gfx10<0x044>;
|
||||
defm DS_MIN_I64 : DS_Real_gfx6_gfx7_gfx10<0x045>;
|
||||
defm DS_MAX_I64 : DS_Real_gfx6_gfx7_gfx10<0x046>;
|
||||
defm DS_MIN_U64 : DS_Real_gfx6_gfx7_gfx10<0x047>;
|
||||
defm DS_MAX_U64 : DS_Real_gfx6_gfx7_gfx10<0x048>;
|
||||
defm DS_AND_B64 : DS_Real_gfx6_gfx7_gfx10<0x049>;
|
||||
defm DS_OR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04a>;
|
||||
defm DS_XOR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04b>;
|
||||
defm DS_MSKOR_B64 : DS_Real_gfx6_gfx7_gfx10<0x04c>;
|
||||
|
||||
defm DS_CONSUME : DS_Real_gfx6_gfx7_gfx10_gfx11<0x03d>;
|
||||
defm DS_APPEND : DS_Real_gfx6_gfx7_gfx10_gfx11<0x03e>;
|
||||
defm DS_ORDERED_COUNT : DS_Real_gfx6_gfx7_gfx10_gfx11<0x03f>;
|
||||
defm DS_ADD_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x040>;
|
||||
defm DS_SUB_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x041>;
|
||||
defm DS_RSUB_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x042>;
|
||||
defm DS_INC_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x043>;
|
||||
defm DS_DEC_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x044>;
|
||||
defm DS_MIN_I64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x045>;
|
||||
defm DS_MAX_I64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x046>;
|
||||
defm DS_MIN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x047>;
|
||||
defm DS_MAX_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x048>;
|
||||
defm DS_AND_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x049>;
|
||||
defm DS_OR_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x04a>;
|
||||
defm DS_XOR_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x04b>;
|
||||
defm DS_MSKOR_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x04c>;
|
||||
|
||||
defm DS_WRITE_B64 : DS_Real_gfx6_gfx7_gfx10<0x04d>;
|
||||
defm DS_WRITE2_B64 : DS_Real_gfx6_gfx7_gfx10<0x04e>;
|
||||
defm DS_WRITE2ST64_B64 : DS_Real_gfx6_gfx7_gfx10<0x04f>;
|
||||
defm DS_CMPST_B64 : DS_Real_gfx6_gfx7_gfx10<0x050>;
|
||||
defm DS_CMPST_F64 : DS_Real_gfx6_gfx7_gfx10<0x051>;
|
||||
defm DS_MIN_F64 : DS_Real_gfx6_gfx7_gfx10<0x052>;
|
||||
defm DS_MAX_F64 : DS_Real_gfx6_gfx7_gfx10<0x053>;
|
||||
defm DS_ADD_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x060>;
|
||||
defm DS_SUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x061>;
|
||||
defm DS_RSUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x062>;
|
||||
defm DS_INC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x063>;
|
||||
defm DS_DEC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x064>;
|
||||
defm DS_MIN_RTN_I64 : DS_Real_gfx6_gfx7_gfx10<0x065>;
|
||||
defm DS_MAX_RTN_I64 : DS_Real_gfx6_gfx7_gfx10<0x066>;
|
||||
defm DS_MIN_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x067>;
|
||||
defm DS_MAX_RTN_U64 : DS_Real_gfx6_gfx7_gfx10<0x068>;
|
||||
defm DS_AND_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x069>;
|
||||
defm DS_OR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06a>;
|
||||
defm DS_XOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06b>;
|
||||
defm DS_MSKOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06c>;
|
||||
|
||||
defm DS_MIN_F64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x052>;
|
||||
defm DS_MAX_F64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x053>;
|
||||
defm DS_ADD_RTN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x060>;
|
||||
defm DS_SUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x061>;
|
||||
defm DS_RSUB_RTN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x062>;
|
||||
defm DS_INC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x063>;
|
||||
defm DS_DEC_RTN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x064>;
|
||||
defm DS_MIN_RTN_I64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x065>;
|
||||
defm DS_MAX_RTN_I64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x066>;
|
||||
defm DS_MIN_RTN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x067>;
|
||||
defm DS_MAX_RTN_U64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x068>;
|
||||
defm DS_AND_RTN_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x069>;
|
||||
defm DS_OR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x06a>;
|
||||
defm DS_XOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x06b>;
|
||||
defm DS_MSKOR_RTN_B64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x06c>;
|
||||
|
||||
defm DS_WRXCHG_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06d>;
|
||||
defm DS_WRXCHG2_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06e>;
|
||||
defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
|
||||
defm DS_CMPST_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x070>;
|
||||
defm DS_CMPST_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x071>;
|
||||
defm DS_MIN_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x072>;
|
||||
defm DS_MAX_RTN_F64 : DS_Real_gfx6_gfx7_gfx10<0x073>;
|
||||
|
||||
defm DS_MIN_RTN_F64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x072>;
|
||||
defm DS_MAX_RTN_F64 : DS_Real_gfx6_gfx7_gfx10_gfx11<0x073>;
|
||||
|
||||
defm DS_READ_B64 : DS_Real_gfx6_gfx7_gfx10<0x076>;
|
||||
defm DS_READ2_B64 : DS_Real_gfx6_gfx7_gfx10<0x077>;
|
||||
defm DS_READ2ST64_B64 : DS_Real_gfx6_gfx7_gfx10<0x078>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,127 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck --check-prefix=GFX11 %s
|
||||
|
||||
ds_write_b32 v0, v1
|
||||
// GFX11: encoding: [0x00,0x00,0x34,0xd8,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_write2_b32 v0, v1, v2
|
||||
// GFX11: encoding: [0x00,0x00,0x38,0xd8,0x00,0x01,0x02,0x00]
|
||||
|
||||
ds_write2st64_b32 v0, v1, v2
|
||||
// GFX11: encoding: [0x00,0x00,0x3c,0xd8,0x00,0x01,0x02,0x00]
|
||||
|
||||
ds_write_b8 v0, v1
|
||||
// GFX11: encoding: [0x00,0x00,0x78,0xd8,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_write_b16 v0, v1
|
||||
// GFX11: encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
|
||||
|
||||
ds_wrxchg_rtn_b32 v0, v1, v2
|
||||
// GFX11: encoding: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x00]
|
||||
|
||||
ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0xfe]
|
||||
|
||||
ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0xfe]
|
||||
|
||||
ds_read_b32 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0xfe]
|
||||
|
||||
ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0xfe]
|
||||
|
||||
ds_read_i8 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_u8 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_i16 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_u16 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_write_b64 v1, v[254:255] offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x34,0xd9,0x01,0xfe,0x00,0x00]
|
||||
|
||||
ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0x38,0xd9,0x01,0xfe,0x03,0x00]
|
||||
|
||||
ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0x3c,0xd9,0x01,0xfe,0x03,0x00]
|
||||
|
||||
ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0xfe]
|
||||
|
||||
ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0xfc]
|
||||
|
||||
ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0xfc]
|
||||
|
||||
ds_read_b64 v[254:255], v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0xfe]
|
||||
|
||||
ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0xfc]
|
||||
|
||||
ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
|
||||
// GFX11: encoding: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0xfc]
|
||||
|
||||
ds_write_b8_d16_hi v1, v2
|
||||
// GFX11: encoding: [0x00,0x00,0x80,0xda,0x01,0x02,0x00,0x00]
|
||||
|
||||
ds_write_b16_d16_hi v1, v2
|
||||
// GFX11: encoding: [0x00,0x00,0x84,0xda,0x01,0x02,0x00,0x00]
|
||||
|
||||
ds_read_u8_d16 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x88,0xda,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_u8_d16_hi v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x8c,0xda,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_i8_d16 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x90,0xda,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_i8_d16_hi v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x94,0xda,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_u16_d16 v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x98,0xda,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_read_u16_d16_hi v255, v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x9c,0xda,0x01,0x00,0x00,0xff]
|
||||
|
||||
ds_write_addtid_b32 v255 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00]
|
||||
|
||||
ds_read_addtid_b32 v255 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff]
|
||||
|
||||
ds_write_b96 v1, v[253:255] offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x78,0xdb,0x01,0xfd,0x00,0x00]
|
||||
|
||||
ds_write_b128 v1, v[252:255] offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00]
|
||||
|
||||
ds_read_b96 v[253:255], v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0xfd]
|
||||
|
||||
ds_read_b128 v[252:255], v1 offset:65535
|
||||
// GFX11: encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc]
|
||||
|
||||
ds_add_gs_reg_rtn v[5:6], v255 offset:127 gds
|
||||
// GFX11: encoding: [0x7f,0x00,0xea,0xd9,0x00,0xff,0x00,0x05]
|
||||
|
||||
ds_add_gs_reg_rtn v[5:6], v255 gds
|
||||
// GFX11: encoding: [0x00,0x00,0xea,0xd9,0x00,0xff,0x00,0x05]
|
||||
|
||||
ds_sub_gs_reg_rtn v[5:6], v255 offset:127 gds
|
||||
// GFX11: encoding: [0x7f,0x00,0xee,0xd9,0x00,0xff,0x00,0x05]
|
||||
|
||||
ds_sub_gs_reg_rtn v[5:6], v255 gds
|
||||
// GFX11: encoding: [0x00,0x00,0xee,0xd9,0x00,0xff,0x00,0x05]
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue