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Reformat. 

llvm-svn: 236601
This commit is contained in:
NAKAMURA Takumi 2015-05-06 14:03:22 +00:00
parent d7c0be9c42
commit e452998b4b
3 changed files with 6 additions and 7 deletions
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2
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -1030,7 +1030,7 @@ public:
SDNodeFlags Flags;
BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
SDValue X, SDValue Y)
: BinarySDNode(Opc, Order, dl, VTs, X, Y), Flags() { }
: BinarySDNode(Opc, Order, dl, VTs, X, Y), Flags() {}
static bool classof(const SDNode *N) {
return isBinOpWithFlags(N->getOpcode());
}

7
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -515,10 +515,9 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
case ISD::SUB:
case ISD::SHL: {
const BinaryWithFlagsSDNode *BinNode = cast<BinaryWithFlagsSDNode>(N);
AddBinaryNodeIDCustom(ID, N->getOpcode(),
BinNode->Flags.hasNoUnsignedWrap(),
BinNode->Flags.hasNoSignedWrap(),
BinNode->Flags.hasExact());
AddBinaryNodeIDCustom(
ID, N->getOpcode(), BinNode->Flags.hasNoUnsignedWrap(),
BinNode->Flags.hasNoSignedWrap(), BinNode->Flags.hasExact());
break;
}
case ISD::ATOMIC_CMP_SWAP:

4
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -2658,8 +2658,8 @@ SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
unsigned ShAmt = d.countTrailingZeros();
if (ShAmt) {
// TODO: For UDIV use SRL instead of SRA.
SDValue Amt = DAG.getConstant(ShAmt, dl,
getShiftAmountTy(Op1.getValueType()));
SDValue Amt =
DAG.getConstant(ShAmt, dl, getShiftAmountTy(Op1.getValueType()));
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
true);
d = d.ashr(ShAmt);