forked from OSchip/llvm-project
AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
bc763c42bb
commit
e4464bf3d4
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@ -100,6 +100,7 @@ def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
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def : GINodeEquiv<G_CTPOP, ctpop>;
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def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
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def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
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def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
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def : GINodeEquiv<G_FCEIL, fceil>;
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def : GINodeEquiv<G_FCOS, fcos>;
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def : GINodeEquiv<G_FSIN, fsin>;
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@ -484,7 +484,7 @@ bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
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const unsigned SrcSize = SrcTy.getSizeInBits();
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if (SrcSize < 32)
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return false;
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return selectImpl(MI, *CoverageInfo);
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const DebugLoc &DL = MI.getDebugLoc();
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const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
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@ -158,20 +158,30 @@ def brtarget : Operand<OtherVT>;
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class HasOneUseUnaryOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0),
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(op $src0),
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[{ return N->hasOneUse(); }]
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>;
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[{ return N->hasOneUse(); }]> {
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let GISelPredicateCode = [{
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return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
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}];
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}
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class HasOneUseBinOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1),
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(op $src0, $src1),
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[{ return N->hasOneUse(); }]
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>;
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[{ return N->hasOneUse(); }]> {
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let GISelPredicateCode = [{
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return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
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}];
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}
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class HasOneUseTernaryOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1, node:$src2),
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(op $src0, $src1, $src2),
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[{ return N->hasOneUse(); }]
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>;
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[{ return N->hasOneUse(); }]> {
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let GISelPredicateCode = [{
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return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
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}];
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}
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let Properties = [SDNPCommutative, SDNPAssociative] in {
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def smax_oneuse : HasOneUseBinOp<smax>;
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@ -1793,54 +1793,59 @@ def : ExpPattern<AMDGPUexport_done, i32, EXP_DONE>;
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// COPY is workaround tablegen bug from multiple outputs
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// from S_LSHL_B32's multiple outputs from implicit scc def.
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def : GCNPat <
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(v2i16 (build_vector (i16 0), i16:$src1)),
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(v2i16 (COPY (S_LSHL_B32 i16:$src1, (i16 16))))
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(v2i16 (build_vector (i16 0), (i16 SReg_32:$src1))),
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(S_LSHL_B32 SReg_32:$src1, (i16 16))
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>;
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def : GCNPat <
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(v2i16 (build_vector i16:$src0, (i16 undef))),
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(v2i16 (COPY $src0))
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(v2i16 (build_vector (i16 SReg_32:$src0), (i16 undef))),
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(COPY_TO_REGCLASS SReg_32:$src0, SReg_32)
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>;
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def : GCNPat <
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(v2i16 (build_vector (i16 VGPR_32:$src0), (i16 undef))),
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(COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32)
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>;
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def : GCNPat <
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(v2f16 (build_vector f16:$src0, (f16 undef))),
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(v2f16 (COPY $src0))
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(COPY $src0)
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>;
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def : GCNPat <
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(v2i16 (build_vector (i16 undef), i16:$src1)),
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(v2i16 (COPY (S_LSHL_B32 $src1, (i32 16))))
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(v2i16 (build_vector (i16 undef), (i16 SReg_32:$src1))),
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(S_LSHL_B32 SReg_32:$src1, (i32 16))
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>;
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def : GCNPat <
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(v2f16 (build_vector (f16 undef), f16:$src1)),
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(v2f16 (COPY (S_LSHL_B32 $src1, (i32 16))))
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(v2f16 (build_vector (f16 undef), (f16 SReg_32:$src1))),
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(S_LSHL_B32 SReg_32:$src1, (i32 16))
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>;
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let SubtargetPredicate = HasVOP3PInsts in {
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def : GCNPat <
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(v2i16 (build_vector i16:$src0, i16:$src1)),
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(v2i16 (S_PACK_LL_B32_B16 $src0, $src1))
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(v2i16 (build_vector (i16 SReg_32:$src0), (i16 SReg_32:$src1))),
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(S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
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>;
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// With multiple uses of the shift, this will duplicate the shift and
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// increase register pressure.
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def : GCNPat <
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(v2i16 (build_vector i16:$src0, (i16 (trunc (srl_oneuse i32:$src1, (i32 16)))))),
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(v2i16 (S_PACK_LH_B32_B16 i16:$src0, i32:$src1))
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(v2i16 (build_vector (i16 SReg_32:$src0), (i16 (trunc (srl_oneuse SReg_32:$src1, (i32 16)))))),
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(v2i16 (S_PACK_LH_B32_B16 SReg_32:$src0, SReg_32:$src1))
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>;
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def : GCNPat <
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(v2i16 (build_vector (i16 (trunc (srl_oneuse i32:$src0, (i32 16)))),
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(i16 (trunc (srl_oneuse i32:$src1, (i32 16)))))),
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(v2i16 (S_PACK_HH_B32_B16 $src0, $src1))
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(v2i16 (build_vector (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))),
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(i16 (trunc (srl_oneuse SReg_32:$src1, (i32 16)))))),
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(S_PACK_HH_B32_B16 SReg_32:$src0, SReg_32:$src1)
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>;
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// TODO: Should source modifiers be matched to v_pack_b32_f16?
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def : GCNPat <
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(v2f16 (build_vector f16:$src0, f16:$src1)),
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(v2f16 (S_PACK_LL_B32_B16 $src0, $src1))
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(v2f16 (build_vector (f16 SReg_32:$src0), (f16 SReg_32:$src1))),
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(S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
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>;
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} // End SubtargetPredicate = HasVOP3PInsts
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@ -0,0 +1,239 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
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---
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name: test_build_vector_s_v2s16_s_s16_s_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_s_v2s16_s_s16_s_s16
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s16) = G_TRUNC %0
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%3:sgpr(s16) = G_TRUNC %1
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%4:sgpr(<2 x s16>) = G_BUILD_VECTOR %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: test_build_vector_s_pack_lh
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_s_pack_lh
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_CONSTANT i32 16
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%3:sgpr(s32) = G_LSHR %1, %2
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%4:sgpr(s16) = G_TRUNC %0
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%5:sgpr(s16) = G_TRUNC %3
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%6:sgpr(<2 x s16>) = G_BUILD_VECTOR %4, %5
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S_ENDPGM 0, implicit %6
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...
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# There is no s_pack_hl_b32
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---
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name: test_build_vector_s_pack_lh_swapped
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_s_pack_lh_swapped
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
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; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[COPY]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_CONSTANT i32 16
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%3:sgpr(s32) = G_LSHR %1, %2
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%4:sgpr(s16) = G_TRUNC %0
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%5:sgpr(s16) = G_TRUNC %3
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%6:sgpr(<2 x s16>) = G_BUILD_VECTOR %5, %4
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S_ENDPGM 0, implicit %6
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...
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---
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name: test_build_vector_s_pack_hh
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_s_pack_hh
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_CONSTANT i32 16
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%3:sgpr(s32) = G_LSHR %0, %2
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%4:sgpr(s32) = G_LSHR %1, %2
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%5:sgpr(s16) = G_TRUNC %3
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%6:sgpr(s16) = G_TRUNC %4
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%7:sgpr(<2 x s16>) = G_BUILD_VECTOR %5, %6
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S_ENDPGM 0, implicit %7
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...
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# TODO: Should this use an and instead?
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---
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name: test_build_vector_s_v2s16_s_s16_s_0_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_s_v2s16_s_s16_s_0_s16
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s16) = G_CONSTANT i16 0
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%3:sgpr(<2 x s16>) = G_BUILD_VECTOR %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: test_build_vector_s_v2s16_s_0_s16_s_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_s_v2s16_s_0_s16_s_s16
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], 16, implicit-def $scc
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; GFX9: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_CONSTANT i16 0
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%2:sgpr(s16) = G_TRUNC %0
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%3:sgpr(<2 x s16>) = G_BUILD_VECTOR %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: test_build_vector_v_v2s16_v_s16_s_undef_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX9-LABEL: name: test_build_vector_v_v2s16_v_s16_s_undef_s16
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; GFX9: liveins: $vgpr0
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: S_ENDPGM 0, implicit [[COPY]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:sgpr(s16) = G_IMPLICIT_DEF
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%3:vgpr(<2 x s16>) = G_BUILD_VECTOR %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: test_build_vector_s_v2s16_s_s16_s_undef_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_s_v2s16_s_s16_s_undef_s16
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s16) = G_IMPLICIT_DEF
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%3:sgpr(<2 x s16>) = G_BUILD_VECTOR %1, %2
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S_ENDPGM 0, implicit %3
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...
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---
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name: test_build_vector_s_v2s16_s_undef_s16_s_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_s_v2s16_s_undef_s16_s_s16
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], 16, implicit-def $scc
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; GFX9: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_IMPLICIT_DEF
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%2:sgpr(s16) = G_TRUNC %0
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%3:sgpr(<2 x s16>) = G_BUILD_VECTOR %1, %2
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S_ENDPGM 0, implicit %3
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...
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