forked from OSchip/llvm-project
[AArch64][x86] add tests for add-with-overflow folds; NFC
There's a generic combine for these, but no test coverage. It's not clear if this is actually a good fold. The combine was added with D58874, but it has a bug that can cause crashing ( https://llvm.org/PR51238 ).
This commit is contained in:
Sanjay Patel
parent
bcc83a2e83
commit
e427077ec1
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@ -223,4 +223,48 @@ test6:
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ret:
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ret void
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}
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declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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define i1 @sadd_add(i32 %a, i32 %b, i32* %p) {
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; CHECK-LABEL: sadd_add:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: cmn w8, w1
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; CHECK-NEXT: cset w8, vs
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; CHECK-NEXT: sub w9, w1, w0
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: str w9, [x2]
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; CHECK-NEXT: ret
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%nota = xor i32 %a, -1
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%a0 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %nota, i32 %b)
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%e0 = extractvalue {i32, i1} %a0, 0
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%e1 = extractvalue {i32, i1} %a0, 1
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%res = add i32 %e0, 1
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store i32 %res, i32* %p
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ret i1 %e1
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}
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declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)
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define i1 @uadd_add(i8 %a, i8 %b, i8* %p) {
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; CHECK-LABEL: uadd_add:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: and w8, w8, #0xff
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; CHECK-NEXT: add w8, w8, w1, uxtb
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; CHECK-NEXT: lsr w8, w8, #8
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; CHECK-NEXT: sub w9, w1, w0
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: strb w9, [x2]
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; CHECK-NEXT: ret
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%nota = xor i8 %a, -1
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%a0 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %nota, i8 %b)
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%e0 = extractvalue {i8, i1} %a0, 0
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%e1 = extractvalue {i8, i1} %a0, 1
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%res = add i8 %e0, 1
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store i8 %res, i8* %p
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ret i1 %e1
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}
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; TODO: adds/subs
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@ -1,16 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
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; fold (add x, 0) -> x
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define <4 x i32> @combine_vec_add_to_zero(<4 x i32> %a) {
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; SSE-LABEL: combine_vec_add_to_zero:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_add_to_zero:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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; CHECK-LABEL: combine_vec_add_to_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = add <4 x i32> %a, zeroinitializer
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ret <4 x i32> %1
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}
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@ -352,17 +348,11 @@ define <4 x i32> @combine_vec_add_sextinreg(<4 x i32> %a0, <4 x i32> %a1) {
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; (add (add (xor a, -1), b), 1) -> (sub b, a)
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define i32 @combine_add_add_not(i32 %a, i32 %b) {
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; SSE-LABEL: combine_add_add_not:
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; SSE: # %bb.0:
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; SSE-NEXT: movl %esi, %eax
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; SSE-NEXT: subl %edi, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_add_add_not:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %esi, %eax
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; AVX-NEXT: subl %edi, %eax
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; AVX-NEXT: retq
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; CHECK-LABEL: combine_add_add_not:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: subl %edi, %eax
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; CHECK-NEXT: retq
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%nota = xor i32 %a, -1
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%add = add i32 %nota, %b
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%r = add i32 %add, 1
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@ -385,3 +375,45 @@ define <4 x i32> @combine_vec_add_add_not(<4 x i32> %a, <4 x i32> %b) {
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%r = add <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %r
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}
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declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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define i1 @sadd_add(i32 %a, i32 %b, i32* %p) {
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; CHECK-LABEL: sadd_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: addl %esi, %eax
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; CHECK-NEXT: seto %al
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; CHECK-NEXT: subl %edi, %esi
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; CHECK-NEXT: movl %esi, (%rdx)
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; CHECK-NEXT: retq
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%nota = xor i32 %a, -1
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%a0 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %nota, i32 %b)
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%e0 = extractvalue {i32, i1} %a0, 0
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%e1 = extractvalue {i32, i1} %a0, 1
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%res = add i32 %e0, 1
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store i32 %res, i32* %p
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ret i1 %e1
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}
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declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)
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define i1 @uadd_add(i8 %a, i8 %b, i8* %p) {
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; CHECK-LABEL: uadd_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: notb %al
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; CHECK-NEXT: addb %sil, %al
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: subb %dil, %sil
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; CHECK-NEXT: movb %sil, (%rdx)
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; CHECK-NEXT: retq
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%nota = xor i8 %a, -1
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%a0 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %nota, i8 %b)
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%e0 = extractvalue {i8, i1} %a0, 0
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%e1 = extractvalue {i8, i1} %a0, 1
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%res = add i8 %e0, 1
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store i8 %res, i8* %p
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ret i1 %e1
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}
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