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[RISCV] Verify consistency of a couple TSFlags related to vector operands 

Various bits of existing code assume the presence of one operand implies the presence of another.  Add verifier rules to catch violations.

Differential Revision: https://reviews.llvm.org/D133810
This commit is contained in:
Philip Reames 2022-09-22 08:27:23 -07:00 committed by Philip Reames
parent bf7c7696fe
commit e41765aa4d
1 changed files with 8 additions and 0 deletions
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8
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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@ -1237,6 +1237,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
return false;
}
}
if (!RISCVII::hasSEWOp(TSFlags)) {
ErrInfo = "VL operand w/o SEW operand?";
return false;
}
}
if (RISCVII::hasSEWOp(TSFlags)) {
unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
@ -1258,6 +1262,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
ErrInfo = "Invalid Policy Value";
return false;
}
if (!RISCVII::hasVLOp(TSFlags)) {
ErrInfo = "policy operand w/o VL operand?";
return false;
}
}
return true;