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Add support for the 'c' constraint. 

Patch by Jack Carter.

llvm-svn: 156293
This commit is contained in:
Eric Christopher 2012-05-07 06:25:10 +00:00
parent c18ae4a3b1
commit e3c494de82
2 changed files with 20 additions and 2 deletions
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14
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -2999,13 +2999,15 @@ getConstraintType(const std::string &Constraint) const
// unless generating MIPS16 code.
// 'y' : Equivalent to r; retained for
// backwards compatibility.
// 'f' : Floating Point registers.
// 'c' : A register suitable for use in an indirect
// jump. This will always be $25 for -mabicalls.
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default : break;
case 'd':
case 'y':
case 'f':
case 'c':
return C_RegisterClass;
}
}
@ -3039,6 +3041,10 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
if (type->isFloatTy())
weight = CW_Register;
break;
case 'c': // $25 for indirect jumps
if (type->isIntegerTy())
weight = CW_SpecificReg;
break;
case 'I': // signed 16 bit immediate
case 'J': // integer zero
case 'K': // unsigned 16 bit immediate
@ -3078,6 +3084,12 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
return std::make_pair(0U, &Mips::FGR64RegClass);
return std::make_pair(0U, &Mips::AFGR64RegClass);
}
break;
case 'c': // register suitable for indirect jump
if (VT == MVT::i32)
return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
assert(VT == MVT::i64 && "Unexpected type.");
return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
}
}
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);

6
llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
View File

@ -23,5 +23,11 @@ entry:
;CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind
; Now c with 1024: make sure register $25 is picked
; CHECK: #APP
; CHECK: addi $25,${{[0-9]+}},1024
; CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
ret i32 0
}