forked from OSchip/llvm-project
fix computation of ambiguous instructions to not ignore the mnemonic.
FWIW, X86 has 254 ambiguous instructions. llvm-svn: 117979
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2ba03aa618
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@ -411,6 +411,10 @@ struct MatchableInfo {
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/// ambiguously match the same set of operands as \arg RHS (without being a
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/// ambiguously match the same set of operands as \arg RHS (without being a
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/// strictly superior match).
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/// strictly superior match).
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bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
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bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) {
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// The primary comparator is the instruction mnemonic.
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if (Tokens[0] != RHS.Tokens[0])
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return false;
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// The number of operands is unambiguous.
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// The number of operands is unambiguous.
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if (Operands.size() != RHS.Operands.size())
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if (Operands.size() != RHS.Operands.size())
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return false;
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return false;
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@ -849,8 +853,8 @@ BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
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}
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}
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void AsmMatcherInfo::BuildOperandClasses() {
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void AsmMatcherInfo::BuildOperandClasses() {
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std::vector<Record*> AsmOperands;
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std::vector<Record*> AsmOperands =
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AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
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Records.getAllDerivedDefinitions("AsmOperandClass");
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// Pre-populate AsmOperandClasses map.
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// Pre-populate AsmOperandClasses map.
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for (std::vector<Record*>::iterator it = AsmOperands.begin(),
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for (std::vector<Record*>::iterator it = AsmOperands.begin(),
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@ -1127,7 +1131,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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}
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}
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}
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}
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std::sort(MIOperandList.begin(), MIOperandList.end());
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array_pod_sort(MIOperandList.begin(), MIOperandList.end());
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// Compute the total number of operands.
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// Compute the total number of operands.
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unsigned NumMIOperands = 0;
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unsigned NumMIOperands = 0;
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