forked from OSchip/llvm-project
add andn/orn/xorn patterns. This allows us to compile this:
long %test(ubyte, short, long %X, long %Y) { %A = xor long %X, -1 %B = and long %Y, %A ret long %B } to this: test: save -96, %sp, %sp andn %i4, %i2, %i0 andn %i5, %i3, %i1 restore %g0, %g0, %g0 retl nop instead of this: test: save -96, %sp, %sp xor %i2, -1, %l0 xor %i3, -1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop The simpleisel emits: :( test: save -96, %sp, %sp or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l1 xor %i2, %l0, %l0 xor %i3, %l1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop llvm-svn: 24793
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@ -250,7 +250,8 @@ def ANDCCri : F3_2<2, 0b010001,
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"andcc $b, $c, $dst", []>;
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def ANDNrr : F3_1<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andn $b, $c, $dst", []>;
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"andn $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
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def ANDNri : F3_2<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andn $b, $c, $dst", []>;
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@ -276,7 +277,8 @@ def ORCCri : F3_2<2, 0b010010,
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"orcc $b, $c, $dst", []>;
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def ORNrr : F3_1<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orn $b, $c, $dst", []>;
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"orn $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
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def ORNri : F3_2<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orn $b, $c, $dst", []>;
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@ -302,7 +304,8 @@ def XORCCri : F3_2<2, 0b010011,
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"xorcc $b, $c, $dst", []>;
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def XNORrr : F3_1<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst", []>;
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"xnor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
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def XNORri : F3_2<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnor $b, $c, $dst", []>;
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