forked from OSchip/llvm-project
AMDGPU: Use rcp for fdiv 1, x with fpmath metadata
Using rcp should be OK for safe math usually, so this should not be replacing the original fdiv. llvm-svn: 276823
This commit is contained in:
Matt Arsenault
parent
685e8ff953
commit
e3862cdc93
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@ -76,7 +76,7 @@ static bool shouldKeepFDivF32(Value *Num, bool UnsafeDiv) {
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return false;
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// Reciprocal f32 is handled separately without denormals.
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return UnsafeDiv && CNum->isExactlyValue(+1.0);
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return UnsafeDiv || CNum->isExactlyValue(+1.0);
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}
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// Insert an intrinsic for fast fdiv for safe math situations where we can
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@ -45,6 +45,7 @@ define void @fdiv_fpmath(float addrspace(1)* %out, float %a, float %b) #1 {
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; CHECK-LABEL: @rcp_fdiv_fpmath(
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; CHECK: %no.md = fdiv float 1.000000e+00, %x{{$}}
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; CHECK: %md.25ulp = fdiv float 1.000000e+00, %x, !fpmath !0
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; CHECK: %md.half.ulp = fdiv float 1.000000e+00, %x, !fpmath !1
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; CHECK: %arcp.no.md = fdiv arcp float 1.000000e+00, %x{{$}}
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; CHECK: %arcp.25ulp = fdiv arcp float 1.000000e+00, %x, !fpmath !0
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@ -54,6 +55,9 @@ define void @rcp_fdiv_fpmath(float addrspace(1)* %out, float %x) #1 {
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%no.md = fdiv float 1.0, %x
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store volatile float %no.md, float addrspace(1)* %out
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%md.25ulp = fdiv float 1.0, %x, !fpmath !0
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store volatile float %md.25ulp, float addrspace(1)* %out
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%md.half.ulp = fdiv float 1.0, %x, !fpmath !1
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store volatile float %md.half.ulp, float addrspace(1)* %out
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@ -146,13 +150,13 @@ define void @rcp_fdiv_fpmath_vector(<2 x float> addrspace(1)* %out, <2 x float>
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; CHECK: %[[X0:[0-9]+]] = extractelement <2 x float> %x, i64 0
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; CHECK: fdiv arcp float 1.000000e+00, %[[X0]], !fpmath !0
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; CHECK: %[[X1:[0-9]+]] = extractelement <2 x float> %x, i64 1
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; CHECK: call arcp float @llvm.amdgcn.fdiv.fast(float 2.000000e+00, float %[[X1]]), !fpmath !0
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; CHECK: fdiv arcp float 2.000000e+00, %[[X1]], !fpmath !0
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; CHECK: store volatile <2 x float> %arcp.25ulp
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; CHECK: %[[X0:[0-9]+]] = extractelement <2 x float> %x, i64 0
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; CHECK: fdiv fast float 1.000000e+00, %[[X0]], !fpmath !0
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; CHECK: %[[X1:[0-9]+]] = extractelement <2 x float> %x, i64 1
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; CHECK: call fast float @llvm.amdgcn.fdiv.fast(float 2.000000e+00, float %[[X1]]), !fpmath !0
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; CHECK: fdiv fast float 2.000000e+00, %[[X1]], !fpmath !0
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; CHECK: store volatile <2 x float> %fast.25ulp
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define void @rcp_fdiv_fpmath_vector_nonsplat(<2 x float> addrspace(1)* %out, <2 x float> %x) #1 {
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%no.md = fdiv <2 x float> <float 1.0, float 2.0>, %x
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@ -1,11 +1,96 @@
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG-SAFE -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FIXME: Evergreen only ever does unsafe fp math.
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; FUNC-LABEL: {{^}}rcp_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
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define void @rcp_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv float 1.0, %src
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_fast_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_fast_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv fast float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_arcp_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_arcp_ulp25_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%rcp = fdiv arcp float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_global_fast_ulp25_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_global_fast_ulp25_pat_f32(float addrspace(1)* %out, float %src) #2 {
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%rcp = fdiv float 1.0, %src, !fpmath !0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_fabs_pat_f32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], |[[SRC]]|
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; GCN: buffer_store_dword [[RCP]]
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; EG: RECIP_IEEE
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define void @rcp_fabs_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%src.fabs = call float @llvm.fabs.f32(float %src)
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%rcp = fdiv float 1.0, %src.fabs
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FIXME: fneg folded into constant 1
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; FUNC-LABEL: {{^}}rcp_fabs_fneg_pat_f32:
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define void @rcp_fabs_fneg_pat_f32(float addrspace(1)* %out, float %src) #0 {
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%src.fabs = call float @llvm.fabs.f32(float %src)
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%src.fabs.fneg = fsub float -0.0, %src.fabs
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%rcp = fdiv float 1.0, %src.fabs.fneg
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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declare float @llvm.fabs.f32(float) #1
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attributes #0 = { nounwind "unsafe-fp-math"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "unsafe-fp-math"="true" }
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!0 = !{float 2.500000e+00}
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@ -1,13 +0,0 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define amdgpu_ps void @test(<4 x float> inreg %reg0) {
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%r0 = extractelement <4 x float> %reg0, i32 0
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%r1 = fdiv float 1.0, %r0
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%vec = insertelement <4 x float> undef, float %r1, i32 0
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call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
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ret void
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}
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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