forked from OSchip/llvm-project
Fix some corner cases with vectors in copyToRegs and copyFromRegs.
llvm-svn: 42907
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4f056f3c10
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@ -648,7 +648,15 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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if (MVT::isVector(PartVT)) {
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assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
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return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
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return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
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}
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if (MVT::isVector(ValueVT)) {
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assert(NumParts == 1 &&
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MVT::getVectorElementType(ValueVT) == PartVT &&
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MVT::getVectorNumElements(ValueVT) == 1 &&
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"Only trivial scalar-to-vector conversions should get here!");
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return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
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}
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if (MVT::isInteger(PartVT) &&
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@ -746,6 +754,13 @@ static void getCopyToParts(SelectionDAG &DAG,
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assert(MVT::isVector(ValueVT) &&
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"Not a vector-vector cast?");
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Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
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} else if (MVT::isVector(ValueVT)) {
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assert(NumParts == 1 &&
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MVT::getVectorElementType(ValueVT) == PartVT &&
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MVT::getVectorNumElements(ValueVT) == 1 &&
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"Only trivial vector-to-scalar conversions should get here!");
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Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
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DAG.getConstant(0, PtrVT));
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} else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
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if (PartVT < ValueVT)
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Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
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