maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

remove broken SRA/rlwimi case 

llvm-svn: 23746
This commit is contained in:
Chris Lattner 2005-10-15 19:04:48 +00:00
parent 6f3b954662
commit e33870d154
1 changed files with 2 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
llvm/lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -145,7 +145,7 @@ static bool isRotateAndMask(unsigned Opcode, unsigned Shift, unsigned Mask,
if (IsShiftMask) Mask = Mask << Shift;
// determine which bits are made indeterminant by shift
Indeterminant = ~(0xFFFFFFFFu << Shift);
} else if (Opcode == ISD::SRA || Opcode == ISD::SRL) { // shift rights
} else if (Opcode == ISD::SRL) { // shift rights
// apply shift to mask if it comes first
if (IsShiftMask) Mask = Mask >> Shift;
// determine which bits are made indeterminant by shift
@ -1125,17 +1125,8 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
case ISD::SRA:
if (isIntImmediate(N.getOperand(1), Tmp2)) {
unsigned SH, MB, ME;
if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
isRotateAndMask(ISD::SRA, Tmp2, Tmp3, true, SH, MB, ME)) {
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
.addImm(MB).addImm(ME);
return Result;
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 &= 0x1F;
BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2 & 0x1F);
} else {
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));