forked from OSchip/llvm-project
[RISCV] Optimize (add (mul r, c0), c1)
Optimize (add (mul x, c0), c1) ->
(add (mul (add x, c1/c0+1), c0), c1%c0-c0),
if c1/c0+1 and c1%c0-c0 are simm12, while c1 is not.
Optimize (add (mul x, c0), c1) ->
(add (mul (add x, c1/c0-1), c0), c1%c0+c0),
if c1/c0-1 and c1%c0+c0 are simm12, while c1 is not.
Reviewed By: craig.topper, asb
Differential Revision: https://reviews.llvm.org/D111141
This commit is contained in:
Ben Shi
Ben Shi
parent
7c6f5950f0
commit
e32cf690df
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@ -6439,7 +6439,19 @@ static SDValue combineSelectAndUseCommutative(SDNode *N, SelectionDAG &DAG,
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// Transform (add (mul x, c0), c1) ->
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// (add (mul (add x, c1/c0), c0), c1%c0).
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// if c1/c0 and c1%c0 are simm12, while c1 is not.
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// if c1/c0 and c1%c0 are simm12, while c1 is not. A special corner case
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// that should be excluded is when c0*(c1/c0) is simm12, which will lead
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// to an infinite loop in DAGCombine if transformed.
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// Or transform (add (mul x, c0), c1) ->
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// (add (mul (add x, c1/c0+1), c0), c1%c0-c0),
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// if c1/c0+1 and c1%c0-c0 are simm12, while c1 is not. A special corner
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// case that should be excluded is when c0*(c1/c0+1) is simm12, which will
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// lead to an infinite loop in DAGCombine if transformed.
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// Or transform (add (mul x, c0), c1) ->
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// (add (mul (add x, c1/c0-1), c0), c1%c0+c0),
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// if c1/c0-1 and c1%c0+c0 are simm12, while c1 is not. A special corner
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// case that should be excluded is when c0*(c1/c0-1) is simm12, which will
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// lead to an infinite loop in DAGCombine if transformed.
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// Or transform (add (mul x, c0), c1) ->
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// (mul (add x, c1/c0), c0).
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// if c1%c0 is zero, and c1/c0 is simm12 while c1 is not.
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@ -6460,35 +6472,37 @@ static SDValue transformAddImmMulImm(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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int64_t C0 = N0C->getSExtValue();
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int64_t C1 = N1C->getSExtValue();
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if (C0 == -1 || C0 == 0 || C0 == 1 || (C1 / C0) == 0 || isInt<12>(C1) ||
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!isInt<12>(C1 % C0) || !isInt<12>(C1 / C0))
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int64_t CA, CB;
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if (C0 == -1 || C0 == 0 || C0 == 1 || isInt<12>(C1))
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return SDValue();
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// If C0 * (C1 / C0) is a 12-bit integer, this transform will be reversed.
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if (isInt<12>(C0 * (C1 / C0)))
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// Search for proper CA (non-zero) and CB that both are simm12.
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if ((C1 / C0) != 0 && isInt<12>(C1 / C0) && isInt<12>(C1 % C0) &&
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!isInt<12>(C0 * (C1 / C0))) {
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CA = C1 / C0;
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CB = C1 % C0;
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} else if ((C1 / C0 + 1) != 0 && isInt<12>(C1 / C0 + 1) &&
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isInt<12>(C1 % C0 - C0) && !isInt<12>(C0 * (C1 / C0 + 1))) {
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CA = C1 / C0 + 1;
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CB = C1 % C0 - C0;
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} else if ((C1 / C0 - 1) != 0 && isInt<12>(C1 / C0 - 1) &&
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isInt<12>(C1 % C0 + C0) && !isInt<12>(C0 * (C1 / C0 - 1))) {
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CA = C1 / C0 - 1;
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CB = C1 % C0 + C0;
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} else
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return SDValue();
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// Build new nodes (add (mul (add x, c1/c0), c0), c1%c0).
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SDLoc DL(N);
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SDValue New0 = DAG.getNode(ISD::ADD, DL, VT, N0->getOperand(0),
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DAG.getConstant(C1 / C0, DL, VT));
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DAG.getConstant(CA, DL, VT));
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SDValue New1 =
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DAG.getNode(ISD::MUL, DL, VT, New0, DAG.getConstant(C0, DL, VT));
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if ((C1 % C0) == 0)
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return New1;
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return DAG.getNode(ISD::ADD, DL, VT, New1, DAG.getConstant(C1 % C0, DL, VT));
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return DAG.getNode(ISD::ADD, DL, VT, New1, DAG.getConstant(CB, DL, VT));
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}
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static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
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const RISCVSubtarget &Subtarget) {
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// Transform (add (mul x, c0), c1) ->
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// (add (mul (add x, c1/c0), c0), c1%c0).
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// if c1/c0 and c1%c0 are simm12, while c1 is not.
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// Or transform (add (mul x, c0), c1) ->
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// (mul (add x, c1/c0), c0).
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// if c1%c0 is zero, and c1/c0 is simm12 while c1 is not.
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if (SDValue V = transformAddImmMulImm(N, DAG, Subtarget))
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return V;
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// Fold (add (shl x, c0), (shl y, c1)) ->
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// (SLLI (SH*ADD x, y), c0), if c1-c0 equals to [1|2|3].
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if (SDValue V = transformAddShlImm(N, DAG, Subtarget))
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return V;
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// fold (add (select lhs, rhs, cc, 0, y), x) ->
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@ -559,9 +559,9 @@ define i64 @add_mul_combine_infinite_loop(i64 %x) {
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;
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; RV64IMB-LABEL: add_mul_combine_infinite_loop:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a0, a0, 86
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; RV64IMB-NEXT: sh1add a0, a0, a0
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; RV64IMB-NEXT: lui a1, 1
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; RV64IMB-NEXT: addiw a1, a1, -2048
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; RV64IMB-NEXT: addi a1, zero, -16
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; RV64IMB-NEXT: sh3add a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i64 %x, 24
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@ -572,22 +572,20 @@ define i64 @add_mul_combine_infinite_loop(i64 %x) {
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define i32 @mul3000_add8990_a(i32 %x) {
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; RV32IMB-LABEL: mul3000_add8990_a:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a0, a0, 3
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; RV32IMB-NEXT: lui a1, 1
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; RV32IMB-NEXT: addi a1, a1, -1096
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 2
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; RV32IMB-NEXT: addi a1, a1, 798
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: addi a0, a0, -10
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: mul3000_add8990_a:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addiw a0, a0, 3
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; RV64IMB-NEXT: lui a1, 1
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; RV64IMB-NEXT: addiw a1, a1, -1096
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, 798
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: addiw a0, a0, -10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 3000
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%tmp1 = add i32 %tmp0, 8990
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@ -597,22 +595,20 @@ define i32 @mul3000_add8990_a(i32 %x) {
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define signext i32 @mul3000_add8990_b(i32 signext %x) {
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; RV32IMB-LABEL: mul3000_add8990_b:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a0, a0, 3
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; RV32IMB-NEXT: lui a1, 1
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; RV32IMB-NEXT: addi a1, a1, -1096
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 2
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; RV32IMB-NEXT: addi a1, a1, 798
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: addi a0, a0, -10
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: mul3000_add8990_b:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addiw a0, a0, 3
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; RV64IMB-NEXT: lui a1, 1
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; RV64IMB-NEXT: addiw a1, a1, -1096
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, 798
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: addiw a0, a0, -10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 3000
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%tmp1 = add i32 %tmp0, 8990
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@ -637,12 +633,11 @@ define i64 @mul3000_add8990_c(i64 %x) {
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;
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; RV64IMB-LABEL: mul3000_add8990_c:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a0, a0, 3
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; RV64IMB-NEXT: lui a1, 1
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; RV64IMB-NEXT: addiw a1, a1, -1096
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; RV64IMB-NEXT: mul a0, a0, a1
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, 798
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; RV64IMB-NEXT: add a0, a0, a1
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; RV64IMB-NEXT: addi a0, a0, -10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i64 %x, 3000
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%tmp1 = add i64 %tmp0, 8990
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@ -652,22 +647,20 @@ define i64 @mul3000_add8990_c(i64 %x) {
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define i32 @mul3000_sub8990_a(i32 %x) {
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; RV32IMB-LABEL: mul3000_sub8990_a:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a0, a0, -3
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; RV32IMB-NEXT: lui a1, 1
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; RV32IMB-NEXT: addi a1, a1, -1096
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 1048574
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; RV32IMB-NEXT: addi a1, a1, -798
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: addi a0, a0, 10
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: mul3000_sub8990_a:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addiw a0, a0, -3
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; RV64IMB-NEXT: lui a1, 1
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; RV64IMB-NEXT: addiw a1, a1, -1096
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 1048574
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; RV64IMB-NEXT: addiw a1, a1, -798
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: addiw a0, a0, 10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 3000
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%tmp1 = add i32 %tmp0, -8990
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@ -677,22 +670,20 @@ define i32 @mul3000_sub8990_a(i32 %x) {
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define signext i32 @mul3000_sub8990_b(i32 signext %x) {
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; RV32IMB-LABEL: mul3000_sub8990_b:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a0, a0, -3
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; RV32IMB-NEXT: lui a1, 1
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; RV32IMB-NEXT: addi a1, a1, -1096
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 1048574
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; RV32IMB-NEXT: addi a1, a1, -798
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: addi a0, a0, 10
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: mul3000_sub8990_b:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addiw a0, a0, -3
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; RV64IMB-NEXT: lui a1, 1
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; RV64IMB-NEXT: addiw a1, a1, -1096
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 1048574
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; RV64IMB-NEXT: addiw a1, a1, -798
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: addiw a0, a0, 10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 3000
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%tmp1 = add i32 %tmp0, -8990
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@ -718,12 +709,11 @@ define i64 @mul3000_sub8990_c(i64 %x) {
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;
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; RV64IMB-LABEL: mul3000_sub8990_c:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a0, a0, -3
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; RV64IMB-NEXT: lui a1, 1
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; RV64IMB-NEXT: addiw a1, a1, -1096
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; RV64IMB-NEXT: mul a0, a0, a1
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; RV64IMB-NEXT: lui a1, 1048574
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; RV64IMB-NEXT: addiw a1, a1, -798
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; RV64IMB-NEXT: add a0, a0, a1
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; RV64IMB-NEXT: addi a0, a0, 10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i64 %x, 3000
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%tmp1 = add i64 %tmp0, -8990
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@ -733,22 +723,20 @@ define i64 @mul3000_sub8990_c(i64 %x) {
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define i32 @mulneg3000_add8990_a(i32 %x) {
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; RV32IMB-LABEL: mulneg3000_add8990_a:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a0, a0, -3
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; RV32IMB-NEXT: lui a1, 1048575
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; RV32IMB-NEXT: addi a1, a1, 1096
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 2
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; RV32IMB-NEXT: addi a1, a1, 798
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: addi a0, a0, -10
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: mulneg3000_add8990_a:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addiw a0, a0, -3
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; RV64IMB-NEXT: lui a1, 1048575
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; RV64IMB-NEXT: addiw a1, a1, 1096
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, 798
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: addiw a0, a0, -10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, -3000
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%tmp1 = add i32 %tmp0, 8990
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@ -758,22 +746,20 @@ define i32 @mulneg3000_add8990_a(i32 %x) {
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define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
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; RV32IMB-LABEL: mulneg3000_add8990_b:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a0, a0, -3
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; RV32IMB-NEXT: lui a1, 1048575
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; RV32IMB-NEXT: addi a1, a1, 1096
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 2
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; RV32IMB-NEXT: addi a1, a1, 798
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: addi a0, a0, -10
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: mulneg3000_add8990_b:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addiw a0, a0, -3
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; RV64IMB-NEXT: lui a1, 1048575
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; RV64IMB-NEXT: addiw a1, a1, 1096
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, 798
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: addiw a0, a0, -10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, -3000
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%tmp1 = add i32 %tmp0, 8990
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@ -799,12 +785,11 @@ define i64 @mulneg3000_add8990_c(i64 %x) {
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;
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; RV64IMB-LABEL: mulneg3000_add8990_c:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a0, a0, -3
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; RV64IMB-NEXT: lui a1, 1048575
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; RV64IMB-NEXT: addiw a1, a1, 1096
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; RV64IMB-NEXT: mul a0, a0, a1
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, 798
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; RV64IMB-NEXT: add a0, a0, a1
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; RV64IMB-NEXT: addi a0, a0, -10
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; RV64IMB-NEXT: ret
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%tmp0 = mul i64 %x, -3000
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%tmp1 = add i64 %tmp0, 8990
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@ -814,22 +799,20 @@ define i64 @mulneg3000_add8990_c(i64 %x) {
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define i32 @mulneg3000_sub8990_a(i32 %x) {
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; RV32IMB-LABEL: mulneg3000_sub8990_a:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a0, a0, 3
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; RV32IMB-NEXT: lui a1, 1048575
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; RV32IMB-NEXT: addi a1, a1, 1096
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 1048574
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; RV32IMB-NEXT: addi a1, a1, -798
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: addi a0, a0, 10
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; RV32IMB-NEXT: ret
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;
|
||||
; RV64IMB-LABEL: mulneg3000_sub8990_a:
|
||||
; RV64IMB: # %bb.0:
|
||||
; RV64IMB-NEXT: addiw a0, a0, 3
|
||||
; RV64IMB-NEXT: lui a1, 1048575
|
||||
; RV64IMB-NEXT: addiw a1, a1, 1096
|
||||
; RV64IMB-NEXT: mulw a0, a0, a1
|
||||
; RV64IMB-NEXT: lui a1, 1048574
|
||||
; RV64IMB-NEXT: addiw a1, a1, -798
|
||||
; RV64IMB-NEXT: addw a0, a0, a1
|
||||
; RV64IMB-NEXT: addiw a0, a0, 10
|
||||
; RV64IMB-NEXT: ret
|
||||
%tmp0 = mul i32 %x, -3000
|
||||
%tmp1 = add i32 %tmp0, -8990
|
||||
|
|
@ -839,22 +822,20 @@ define i32 @mulneg3000_sub8990_a(i32 %x) {
|
|||
define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
|
||||
; RV32IMB-LABEL: mulneg3000_sub8990_b:
|
||||
; RV32IMB: # %bb.0:
|
||||
; RV32IMB-NEXT: addi a0, a0, 3
|
||||
; RV32IMB-NEXT: lui a1, 1048575
|
||||
; RV32IMB-NEXT: addi a1, a1, 1096
|
||||
; RV32IMB-NEXT: mul a0, a0, a1
|
||||
; RV32IMB-NEXT: lui a1, 1048574
|
||||
; RV32IMB-NEXT: addi a1, a1, -798
|
||||
; RV32IMB-NEXT: add a0, a0, a1
|
||||
; RV32IMB-NEXT: addi a0, a0, 10
|
||||
; RV32IMB-NEXT: ret
|
||||
;
|
||||
; RV64IMB-LABEL: mulneg3000_sub8990_b:
|
||||
; RV64IMB: # %bb.0:
|
||||
; RV64IMB-NEXT: addiw a0, a0, 3
|
||||
; RV64IMB-NEXT: lui a1, 1048575
|
||||
; RV64IMB-NEXT: addiw a1, a1, 1096
|
||||
; RV64IMB-NEXT: mulw a0, a0, a1
|
||||
; RV64IMB-NEXT: lui a1, 1048574
|
||||
; RV64IMB-NEXT: addiw a1, a1, -798
|
||||
; RV64IMB-NEXT: addw a0, a0, a1
|
||||
; RV64IMB-NEXT: addiw a0, a0, 10
|
||||
; RV64IMB-NEXT: ret
|
||||
%tmp0 = mul i32 %x, -3000
|
||||
%tmp1 = add i32 %tmp0, -8990
|
||||
|
|
@ -881,12 +862,11 @@ define i64 @mulneg3000_sub8990_c(i64 %x) {
|
|||
;
|
||||
; RV64IMB-LABEL: mulneg3000_sub8990_c:
|
||||
; RV64IMB: # %bb.0:
|
||||
; RV64IMB-NEXT: addi a0, a0, 3
|
||||
; RV64IMB-NEXT: lui a1, 1048575
|
||||
; RV64IMB-NEXT: addiw a1, a1, 1096
|
||||
; RV64IMB-NEXT: mul a0, a0, a1
|
||||
; RV64IMB-NEXT: lui a1, 1048574
|
||||
; RV64IMB-NEXT: addiw a1, a1, -798
|
||||
; RV64IMB-NEXT: add a0, a0, a1
|
||||
; RV64IMB-NEXT: addi a0, a0, 10
|
||||
; RV64IMB-NEXT: ret
|
||||
%tmp0 = mul i64 %x, -3000
|
||||
%tmp1 = add i64 %tmp0, -8990
|
||||
|
|
|
|||
Loading…
Reference in New Issue