forked from OSchip/llvm-project
Fixed the number translation scheme for the integer condition code registers: it
now works in instructions which require a 2-bit or 3-bit INTcc code. Incidentally, that means that the representation of INTcc registers is now the same in both integer and FP instructions. Thus, code became much simpler and cleaner. llvm-svn: 7185
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@ -327,22 +327,6 @@ void SparcV9CodeEmitter::emitWord(unsigned Val) {
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}
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}
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bool SparcV9CodeEmitter::isFPInstr(MachineInstr &MI) {
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for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (MO.isPhysicalRegister()) {
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unsigned fakeReg = MO.getReg(), realReg, regClass, regType;
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regType = TM.getRegInfo().getRegType(fakeReg);
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// At least map fakeReg into its class
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// fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
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if (regType == UltraSparcRegInfo::FPSingleRegType ||
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regType == UltraSparcRegInfo::FPDoubleRegType)
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return true;
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}
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}
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return false;
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}
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unsigned
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SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
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MachineInstr &MI) {
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@ -386,21 +370,13 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
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return fakeReg;
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}
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case UltraSparcRegInfo::IntCCRegClassID: {
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/* xcc, icc, ccr */
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static const unsigned FPInstrIntCCReg[] = { 6, 4, 2 };
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static const unsigned IntInstrIntCCReg[] = { 2, 0, 2 };
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/* xcc, icc, ccr */
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static const unsigned IntCCReg[] = { 6, 4, 2 };
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if (isFPInstr(MI)) {
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assert(fakeReg < sizeof(FPInstrIntCCReg)/sizeof(FPInstrIntCCReg[0])
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&& "FP CC register out of bounds for FPInstr IntCCReg map");
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DEBUG(std::cerr << "FP instr, IntCC reg: " << FPInstrIntCCReg[fakeReg] << "\n");
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return FPInstrIntCCReg[fakeReg];
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} else {
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assert(fakeReg < sizeof(IntInstrIntCCReg)/sizeof(IntInstrIntCCReg[0])
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&& "Int CC register out of bounds for IntInstr IntCCReg map");
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DEBUG(std::cerr << "FP instr, IntCC reg: " << IntInstrIntCCReg[fakeReg] << "\n");
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return IntInstrIntCCReg[fakeReg];
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}
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assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
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&& "CC register out of bounds for IntCCReg map");
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DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
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return IntCCReg[fakeReg];
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}
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case UltraSparcRegInfo::FloatCCRegClassID: {
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/* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
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@ -580,7 +556,8 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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unsigned fakeReg = MO.getAllocatedRegNum();
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unsigned realRegByClass = getRealRegNum(fakeReg, MI);
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DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
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<< realRegByClass << "\n");
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<< realRegByClass << " (LLC: "
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<< TM.getRegInfo().getUnifiedRegName(fakeReg) << ")\n");
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rv = realRegByClass;
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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@ -47,7 +47,6 @@ private:
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void emitBasicBlock(MachineBasicBlock &MBB);
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void* getGlobalAddress(GlobalValue *V, MachineInstr &MI,
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bool isPCRelative);
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bool isFPInstr(MachineInstr &MI);
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unsigned getRealRegNum(unsigned fakeReg, MachineInstr &MI);
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inline void emitFarCall(uint64_t Addr);
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