forked from OSchip/llvm-project
AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACT
llvm-svn: 326715
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@ -308,6 +308,15 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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break;
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}
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case AMDGPU::G_EXTRACT: {
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unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
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unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
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unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
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OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
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OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
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OpdsMapping[2] = nullptr;
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break;
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}
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case AMDGPU::G_BITCAST: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
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@ -0,0 +1,31 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: extract_lo32_i64_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: extract_lo32_i64_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
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%0:_(s64) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_EXTRACT %0, 0
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...
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---
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name: extract_lo32_i64_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: extract_lo32_i64_v
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_EXTRACT %0, 0
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...
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