forked from OSchip/llvm-project
[X86][SSE] Add pblendw commuted load test case
Reduced test case for the regression caused in D57888/rL353610 llvm-svn: 354360
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@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s
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define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) #0 {
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define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) {
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; CHECK-LABEL: commute_fold_pblendw:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1,2,3],xmm0[4],mem[5,6,7]
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@ -12,7 +12,7 @@ define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) #0 {
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}
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declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone
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define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) #0 {
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define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) {
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; CHECK-LABEL: commute_fold_blendps:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3]
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@ -23,7 +23,7 @@ define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) #0 {
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}
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declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone
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define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) #0 {
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define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) {
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; CHECK-LABEL: commute_fold_blendpd:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]
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@ -33,3 +33,15 @@ define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) #0
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ret <2 x double> %2
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}
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declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone
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define <4 x i32> @commute_fold_blend_v4i32(<4 x i32>* %a, <4 x i32> %b) {
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; CHECK-LABEL: commute_fold_blend_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: paddd %xmm0, %xmm0 ; force integer domain
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = mem[0,1,2,3,4,5],xmm0[6,7]
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; CHECK-NEXT: retq
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%1 = load <4 x i32>, <4 x i32>* %a
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%2 = add <4 x i32> %b, %b
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%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i32> %3
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}
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