forked from OSchip/llvm-project
[AArch64] Add NEON test cases for ISD::ABDS/U.
This commit is contained in:
Paul Walker
parent
718562a469
commit
e30525b6a5
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@ -0,0 +1,381 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; SABD
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;
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define <8 x i8> @sabd_8b(<8 x i8> %a, <8 x i8> %b) #0 {
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; CHECK-LABEL: sabd_8b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%a.sext = sext <8 x i8> %a to <8 x i16>
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%b.sext = sext <8 x i8> %b to <8 x i16>
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%sub = sub <8 x i16> %a.sext, %b.sext
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%abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)
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%trunc = trunc <8 x i16> %abs to <8 x i8>
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ret <8 x i8> %trunc
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}
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define <16 x i8> @sabd_16b(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: sabd_16b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%a.sext = sext <16 x i8> %a to <16 x i16>
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%b.sext = sext <16 x i8> %b to <16 x i16>
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%sub = sub <16 x i16> %a.sext, %b.sext
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%abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)
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%trunc = trunc <16 x i16> %abs to <16 x i8>
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ret <16 x i8> %trunc
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}
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define <4 x i16> @sabd_4h(<4 x i16> %a, <4 x i16> %b) #0 {
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; CHECK-LABEL: sabd_4h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%a.sext = sext <4 x i16> %a to <4 x i32>
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%b.sext = sext <4 x i16> %b to <4 x i32>
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%sub = sub <4 x i32> %a.sext, %b.sext
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%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
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%trunc = trunc <4 x i32> %abs to <4 x i16>
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ret <4 x i16> %trunc
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}
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define <4 x i16> @sabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) #0 {
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; CHECK-LABEL: sabd_4h_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: shl v1.4h, v1.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v1.4h, v1.4h, #8
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; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: abs v0.4h, v0.4h
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; CHECK-NEXT: ret
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%a.sext = sext <4 x i8> %a to <4 x i16>
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%b.sext = sext <4 x i8> %b to <4 x i16>
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%sub = sub <4 x i16> %a.sext, %b.sext
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%abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true)
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ret <4 x i16> %abs
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}
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define <8 x i16> @sabd_8h(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: sabd_8h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%a.sext = sext <8 x i16> %a to <8 x i32>
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%b.sext = sext <8 x i16> %b to <8 x i32>
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%sub = sub <8 x i32> %a.sext, %b.sext
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%abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)
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%trunc = trunc <8 x i32> %abs to <8 x i16>
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ret <8 x i16> %trunc
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}
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define <8 x i16> @sabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) #0 {
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; CHECK-LABEL: sabd_8h_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabdl v0.8h, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%a.sext = sext <8 x i8> %a to <8 x i16>
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%b.sext = sext <8 x i8> %b to <8 x i16>
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%sub = sub <8 x i16> %a.sext, %b.sext
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%abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)
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ret <8 x i16> %abs
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}
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define <2 x i32> @sabd_2s(<2 x i32> %a, <2 x i32> %b) #0 {
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; CHECK-LABEL: sabd_2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%a.sext = sext <2 x i32> %a to <2 x i64>
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%b.sext = sext <2 x i32> %b to <2 x i64>
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%sub = sub <2 x i64> %a.sext, %b.sext
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%abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)
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%trunc = trunc <2 x i64> %abs to <2 x i32>
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ret <2 x i32> %trunc
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}
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define <2 x i32> @sabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) #0 {
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; CHECK-LABEL: sabd_2s_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.2s, v0.2s, #16
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; CHECK-NEXT: shl v1.2s, v1.2s, #16
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; CHECK-NEXT: sshr v0.2s, v0.2s, #16
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; CHECK-NEXT: sshr v1.2s, v1.2s, #16
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; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: abs v0.2s, v0.2s
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; CHECK-NEXT: ret
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%a.sext = sext <2 x i16> %a to <2 x i32>
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%b.sext = sext <2 x i16> %b to <2 x i32>
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%sub = sub <2 x i32> %a.sext, %b.sext
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%abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true)
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ret <2 x i32> %abs
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}
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define <4 x i32> @sabd_4s(<4 x i32> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: sabd_4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%a.sext = sext <4 x i32> %a to <4 x i64>
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%b.sext = sext <4 x i32> %b to <4 x i64>
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%sub = sub <4 x i64> %a.sext, %b.sext
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%abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)
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%trunc = trunc <4 x i64> %abs to <4 x i32>
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ret <4 x i32> %trunc
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}
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define <4 x i32> @sabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) #0 {
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; CHECK-LABEL: sabd_4s_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabdl v0.4s, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%a.sext = sext <4 x i16> %a to <4 x i32>
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%b.sext = sext <4 x i16> %b to <4 x i32>
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%sub = sub <4 x i32> %a.sext, %b.sext
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%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
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ret <4 x i32> %abs
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}
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define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) #0 {
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; CHECK-LABEL: sabd_2d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: fmov x10, d0
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; CHECK-NEXT: mov x9, v1.d[1]
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; CHECK-NEXT: asr x11, x10, #63
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; CHECK-NEXT: asr x12, x8, #63
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; CHECK-NEXT: asr x13, x9, #63
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; CHECK-NEXT: subs x8, x8, x9
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; CHECK-NEXT: fmov x9, d1
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; CHECK-NEXT: sbcs x12, x12, x13
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; CHECK-NEXT: asr x13, x9, #63
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; CHECK-NEXT: subs x9, x10, x9
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; CHECK-NEXT: sbcs x10, x11, x13
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; CHECK-NEXT: cmp x10, #0
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; CHECK-NEXT: cneg x9, x9, lt
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; CHECK-NEXT: cmp x12, #0
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; CHECK-NEXT: cneg x8, x8, lt
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; CHECK-NEXT: fmov d0, x9
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-NEXT: ret
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%a.sext = sext <2 x i64> %a to <2 x i128>
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%b.sext = sext <2 x i64> %b to <2 x i128>
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%sub = sub <2 x i128> %a.sext, %b.sext
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%abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true)
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%trunc = trunc <2 x i128> %abs to <2 x i64>
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ret <2 x i64> %trunc
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}
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define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) #0 {
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; CHECK-LABEL: sabd_2d_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabdl v0.2d, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%a.sext = sext <2 x i32> %a to <2 x i64>
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%b.sext = sext <2 x i32> %b to <2 x i64>
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%sub = sub <2 x i64> %a.sext, %b.sext
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%abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)
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ret <2 x i64> %abs
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}
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;
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; UABD
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;
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define <8 x i8> @uabd_8b(<8 x i8> %a, <8 x i8> %b) #0 {
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; CHECK-LABEL: uabd_8b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%a.zext = zext <8 x i8> %a to <8 x i16>
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%b.zext = zext <8 x i8> %b to <8 x i16>
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%sub = sub <8 x i16> %a.zext, %b.zext
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%abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)
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%trunc = trunc <8 x i16> %abs to <8 x i8>
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ret <8 x i8> %trunc
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}
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define <16 x i8> @uabd_16b(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: uabd_16b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%a.zext = zext <16 x i8> %a to <16 x i16>
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%b.zext = zext <16 x i8> %b to <16 x i16>
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%sub = sub <16 x i16> %a.zext, %b.zext
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%abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)
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%trunc = trunc <16 x i16> %abs to <16 x i8>
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ret <16 x i8> %trunc
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}
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define <4 x i16> @uabd_4h(<4 x i16> %a, <4 x i16> %b) #0 {
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; CHECK-LABEL: uabd_4h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%a.zext = zext <4 x i16> %a to <4 x i32>
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%b.zext = zext <4 x i16> %b to <4 x i32>
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%sub = sub <4 x i32> %a.zext, %b.zext
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%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
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%trunc = trunc <4 x i32> %abs to <4 x i16>
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ret <4 x i16> %trunc
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}
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define <4 x i16> @uabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) #0 {
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; CHECK-LABEL: uabd_4h_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.4h, #255, lsl #8
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; CHECK-NEXT: bic v1.4h, #255, lsl #8
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; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: abs v0.4h, v0.4h
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; CHECK-NEXT: ret
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%a.zext = zext <4 x i8> %a to <4 x i16>
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%b.zext = zext <4 x i8> %b to <4 x i16>
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%sub = sub <4 x i16> %a.zext, %b.zext
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%abs = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %sub, i1 true)
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ret <4 x i16> %abs
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}
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define <8 x i16> @uabd_8h(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: uabd_8h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%a.zext = zext <8 x i16> %a to <8 x i32>
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%b.zext = zext <8 x i16> %b to <8 x i32>
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%sub = sub <8 x i32> %a.zext, %b.zext
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%abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 true)
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%trunc = trunc <8 x i32> %abs to <8 x i16>
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ret <8 x i16> %trunc
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}
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define <8 x i16> @uabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) #0 {
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; CHECK-LABEL: uabd_8h_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabdl v0.8h, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%a.zext = zext <8 x i8> %a to <8 x i16>
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%b.zext = zext <8 x i8> %b to <8 x i16>
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%sub = sub <8 x i16> %a.zext, %b.zext
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%abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true)
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ret <8 x i16> %abs
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}
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define <2 x i32> @uabd_2s(<2 x i32> %a, <2 x i32> %b) #0 {
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; CHECK-LABEL: uabd_2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%a.zext = zext <2 x i32> %a to <2 x i64>
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%b.zext = zext <2 x i32> %b to <2 x i64>
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%sub = sub <2 x i64> %a.zext, %b.zext
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%abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)
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%trunc = trunc <2 x i64> %abs to <2 x i32>
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ret <2 x i32> %trunc
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}
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define <2 x i32> @uabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) #0 {
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; CHECK-LABEL: uabd_2s_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi d2, #0x00ffff0000ffff
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; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
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; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: abs v0.2s, v0.2s
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; CHECK-NEXT: ret
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%a.zext = zext <2 x i16> %a to <2 x i32>
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%b.zext = zext <2 x i16> %b to <2 x i32>
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%sub = sub <2 x i32> %a.zext, %b.zext
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%abs = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %sub, i1 true)
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ret <2 x i32> %abs
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}
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define <4 x i32> @uabd_4s(<4 x i32> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: uabd_4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%a.zext = zext <4 x i32> %a to <4 x i64>
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%b.zext = zext <4 x i32> %b to <4 x i64>
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%sub = sub <4 x i64> %a.zext, %b.zext
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%abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)
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%trunc = trunc <4 x i64> %abs to <4 x i32>
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ret <4 x i32> %trunc
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}
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define <4 x i32> @uabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) #0 {
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; CHECK-LABEL: uabd_4s_promoted_ops:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabdl v0.4s, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%a.zext = zext <4 x i16> %a to <4 x i32>
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%b.zext = zext <4 x i16> %b to <4 x i32>
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%sub = sub <4 x i32> %a.zext, %b.zext
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%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true)
|
||||
ret <4 x i32> %abs
|
||||
}
|
||||
|
||||
define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) #0 {
|
||||
; CHECK-LABEL: uabd_2d:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov x8, v0.d[1]
|
||||
; CHECK-NEXT: fmov x10, d0
|
||||
; CHECK-NEXT: mov x9, v1.d[1]
|
||||
; CHECK-NEXT: subs x8, x8, x9
|
||||
; CHECK-NEXT: fmov x9, d1
|
||||
; CHECK-NEXT: ngcs x11, xzr
|
||||
; CHECK-NEXT: subs x9, x10, x9
|
||||
; CHECK-NEXT: ngcs x10, xzr
|
||||
; CHECK-NEXT: cmp x10, #0
|
||||
; CHECK-NEXT: cneg x9, x9, lt
|
||||
; CHECK-NEXT: cmp x11, #0
|
||||
; CHECK-NEXT: cneg x8, x8, lt
|
||||
; CHECK-NEXT: fmov d0, x9
|
||||
; CHECK-NEXT: fmov d1, x8
|
||||
; CHECK-NEXT: mov v0.d[1], v1.d[0]
|
||||
; CHECK-NEXT: ret
|
||||
%a.zext = zext <2 x i64> %a to <2 x i128>
|
||||
%b.zext = zext <2 x i64> %b to <2 x i128>
|
||||
%sub = sub <2 x i128> %a.zext, %b.zext
|
||||
%abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true)
|
||||
%trunc = trunc <2 x i128> %abs to <2 x i64>
|
||||
ret <2 x i64> %trunc
|
||||
}
|
||||
|
||||
define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) #0 {
|
||||
; CHECK-LABEL: uabd_2d_promoted_ops:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uabdl v0.2d, v0.2s, v1.2s
|
||||
; CHECK-NEXT: ret
|
||||
%a.zext = zext <2 x i32> %a to <2 x i64>
|
||||
%b.zext = zext <2 x i32> %b to <2 x i64>
|
||||
%sub = sub <2 x i64> %a.zext, %b.zext
|
||||
%abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true)
|
||||
ret <2 x i64> %abs
|
||||
}
|
||||
|
||||
declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1)
|
||||
declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)
|
||||
|
||||
declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1)
|
||||
declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
|
||||
declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)
|
||||
|
||||
declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
|
||||
declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
|
||||
declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
|
||||
|
||||
declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
|
||||
declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
|
||||
|
||||
declare <2 x i128> @llvm.abs.v2i128(<2 x i128>, i1)
|
||||
|
||||
attributes #0 = { "target-features"="+neon" }
|
||||
Loading…
Reference in New Issue