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AMDGPU: Guard VOPC instructions against incorrect commute 

Summary:
The added testcase, which triggered this, was derived from a shader-db case
via bugpoint. A separate question is why scalar branching wasn't used.

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19208

llvm-svn: 266825
This commit is contained in:
Nicolai Haehnle 2016-04-19 21:58:22 +00:00
parent 7483937bf0
commit e2dda4f750
2 changed files with 52 additions and 3 deletions
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6
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -944,10 +944,10 @@ MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
MachineOperand &Src1 = MI->getOperand(Src1Idx); MachineOperand &Src1 = MI->getOperand(Src1Idx);
if (isVOP2(*MI)) { if (isVOP2(*MI) || isVOPC(*MI)) {
const MCInstrDesc &InstrDesc = MI->getDesc(); const MCInstrDesc &InstrDesc = MI->getDesc();
// For VOP2 instructions, any operand type is valid to use for src0. Make // For VOP2 and VOPC instructions, any operand type is valid to use for
// sure we can use the src1 as src0. // src0. Make sure we can use the src0 as src1.
// //
// We could be stricter here and only allow commuting if there is a reason // We could be stricter here and only allow commuting if there is a reason
// to do so. i.e. if both operands are VGPRs there is no real benefit, // to do so. i.e. if both operands are VGPRs there is no real benefit,

49
llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll Normal file
View File

@ -0,0 +1,49 @@
; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
target triple = "amdgcn--"
; CHECK-LABEL: {{^}}main:
;
; Test for compilation only. This generated an invalid machine instruction
; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
; of which were in SGPRs.
define amdgpu_vs float @main(i32 %v) {
main_body:
%d1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 960)
%d2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 976)
br i1 undef, label %ENDIF56, label %IF57
IF57: ; preds = %ENDIF
%v.1 = mul i32 %v, 2
br label %ENDIF56
ENDIF56: ; preds = %IF57, %ENDIF
%v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ]
%d1.i = bitcast float %d1 to i32
%cc1 = icmp eq i32 %d1.i, 0
br i1 %cc1, label %ENDIF59, label %IF60
IF60: ; preds = %ENDIF56
%v.3 = mul i32 %v.2, 2
br label %ENDIF59
ENDIF59: ; preds = %IF60, %ENDIF56
%v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ]
%d2.i = bitcast float %d2 to i32
%cc2 = icmp eq i32 %d2.i, 0
br i1 %cc2, label %ENDIF62, label %IF63
IF63: ; preds = %ENDIF59
unreachable
ENDIF62: ; preds = %ENDIF59
%r = bitcast i32 %v.4 to float
ret float %r
}
; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #0
attributes #0 = { nounwind readnone }
attributes #1 = { readnone }