forked from OSchip/llvm-project
[RISCV][NFC] Add additional cmov tests
One or more cmov instructions could be generated for these functions when the Zbt extension is present. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D93768
This commit is contained in:
Michael Munday
Sam Elliott
parent
ed936aad78
commit
e2d3d501ef
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@ -86,15 +86,143 @@ define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind {
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ret i32 %cond
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}
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define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; RV32I-LABEL: cmov_sle_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bge a2, a1, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a3, a0
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: cmov_sle_i32:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: bge a2, a1, .LBB3_2
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; RV32IB-NEXT: # %bb.1:
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; RV32IB-NEXT: mv a3, a0
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; RV32IB-NEXT: .LBB3_2:
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; RV32IB-NEXT: mv a0, a3
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; RV32IB-NEXT: ret
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;
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; RV32IBT-LABEL: cmov_sle_i32:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: bge a2, a1, .LBB3_2
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; RV32IBT-NEXT: # %bb.1:
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; RV32IBT-NEXT: mv a3, a0
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; RV32IBT-NEXT: .LBB3_2:
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; RV32IBT-NEXT: mv a0, a3
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; RV32IBT-NEXT: ret
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%tobool = icmp sle i32 %b, %c
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%cond = select i1 %tobool, i32 %d, i32 %a
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ret i32 %cond
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}
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define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; RV32I-LABEL: cmov_sge_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bge a1, a2, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a3, a0
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: cmov_sge_i32:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: bge a1, a2, .LBB4_2
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; RV32IB-NEXT: # %bb.1:
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; RV32IB-NEXT: mv a3, a0
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; RV32IB-NEXT: .LBB4_2:
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; RV32IB-NEXT: mv a0, a3
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; RV32IB-NEXT: ret
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;
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; RV32IBT-LABEL: cmov_sge_i32:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: bge a1, a2, .LBB4_2
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; RV32IBT-NEXT: # %bb.1:
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; RV32IBT-NEXT: mv a3, a0
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; RV32IBT-NEXT: .LBB4_2:
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; RV32IBT-NEXT: mv a0, a3
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; RV32IBT-NEXT: ret
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%tobool = icmp sge i32 %b, %c
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%cond = select i1 %tobool, i32 %d, i32 %a
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ret i32 %cond
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}
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define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; RV32I-LABEL: cmov_ule_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bgeu a2, a1, .LBB5_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a3, a0
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; RV32I-NEXT: .LBB5_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: cmov_ule_i32:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: bgeu a2, a1, .LBB5_2
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; RV32IB-NEXT: # %bb.1:
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; RV32IB-NEXT: mv a3, a0
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; RV32IB-NEXT: .LBB5_2:
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; RV32IB-NEXT: mv a0, a3
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; RV32IB-NEXT: ret
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;
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; RV32IBT-LABEL: cmov_ule_i32:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: bgeu a2, a1, .LBB5_2
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; RV32IBT-NEXT: # %bb.1:
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; RV32IBT-NEXT: mv a3, a0
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; RV32IBT-NEXT: .LBB5_2:
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; RV32IBT-NEXT: mv a0, a3
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; RV32IBT-NEXT: ret
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%tobool = icmp ule i32 %b, %c
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%cond = select i1 %tobool, i32 %d, i32 %a
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ret i32 %cond
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}
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define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; RV32I-LABEL: cmov_uge_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bgeu a1, a2, .LBB6_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a3, a0
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; RV32I-NEXT: .LBB6_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: cmov_uge_i32:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: bgeu a1, a2, .LBB6_2
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; RV32IB-NEXT: # %bb.1:
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; RV32IB-NEXT: mv a3, a0
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; RV32IB-NEXT: .LBB6_2:
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; RV32IB-NEXT: mv a0, a3
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; RV32IB-NEXT: ret
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;
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; RV32IBT-LABEL: cmov_uge_i32:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: bgeu a1, a2, .LBB6_2
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; RV32IBT-NEXT: # %bb.1:
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; RV32IBT-NEXT: mv a3, a0
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; RV32IBT-NEXT: .LBB6_2:
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; RV32IBT-NEXT: mv a0, a3
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; RV32IBT-NEXT: ret
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%tobool = icmp uge i32 %b, %c
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%cond = select i1 %tobool, i32 %d, i32 %a
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ret i32 %cond
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}
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define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
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; RV32I-LABEL: cmov_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: or a2, a2, a3
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; RV32I-NEXT: beqz a2, .LBB3_2
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; RV32I-NEXT: beqz a2, .LBB7_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a4, a0
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; RV32I-NEXT: mv a5, a1
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: .LBB7_2:
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; RV32I-NEXT: mv a0, a4
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; RV32I-NEXT: mv a1, a5
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; RV32I-NEXT: ret
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@ -117,6 +245,266 @@ define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
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ret i64 %cond
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}
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define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
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; RV32I-LABEL: cmov_sle_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a3, a5, .LBB8_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: slt a2, a5, a3
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; RV32I-NEXT: xori a2, a2, 1
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; RV32I-NEXT: beqz a2, .LBB8_3
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; RV32I-NEXT: j .LBB8_4
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; RV32I-NEXT: .LBB8_2:
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; RV32I-NEXT: sltu a2, a4, a2
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; RV32I-NEXT: xori a2, a2, 1
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; RV32I-NEXT: bnez a2, .LBB8_4
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; RV32I-NEXT: .LBB8_3:
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; RV32I-NEXT: mv a6, a0
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; RV32I-NEXT: mv a7, a1
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; RV32I-NEXT: .LBB8_4:
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; RV32I-NEXT: mv a0, a6
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; RV32I-NEXT: mv a1, a7
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: cmov_sle_i64:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: beq a3, a5, .LBB8_2
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; RV32IB-NEXT: # %bb.1:
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; RV32IB-NEXT: slt a2, a5, a3
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; RV32IB-NEXT: xori a2, a2, 1
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; RV32IB-NEXT: beqz a2, .LBB8_3
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; RV32IB-NEXT: j .LBB8_4
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; RV32IB-NEXT: .LBB8_2:
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; RV32IB-NEXT: sltu a2, a4, a2
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; RV32IB-NEXT: xori a2, a2, 1
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; RV32IB-NEXT: bnez a2, .LBB8_4
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; RV32IB-NEXT: .LBB8_3:
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; RV32IB-NEXT: mv a6, a0
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; RV32IB-NEXT: mv a7, a1
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; RV32IB-NEXT: .LBB8_4:
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; RV32IB-NEXT: mv a0, a6
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; RV32IB-NEXT: mv a1, a7
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; RV32IB-NEXT: ret
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;
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; RV32IBT-LABEL: cmov_sle_i64:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: beq a3, a5, .LBB8_2
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; RV32IBT-NEXT: # %bb.1:
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; RV32IBT-NEXT: slt a2, a5, a3
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; RV32IBT-NEXT: xori a2, a2, 1
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; RV32IBT-NEXT: beqz a2, .LBB8_3
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; RV32IBT-NEXT: j .LBB8_4
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; RV32IBT-NEXT: .LBB8_2:
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; RV32IBT-NEXT: sltu a2, a4, a2
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; RV32IBT-NEXT: xori a2, a2, 1
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; RV32IBT-NEXT: bnez a2, .LBB8_4
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; RV32IBT-NEXT: .LBB8_3:
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; RV32IBT-NEXT: mv a6, a0
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; RV32IBT-NEXT: mv a7, a1
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; RV32IBT-NEXT: .LBB8_4:
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; RV32IBT-NEXT: mv a0, a6
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; RV32IBT-NEXT: mv a1, a7
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; RV32IBT-NEXT: ret
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%tobool = icmp sle i64 %b, %c
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%cond = select i1 %tobool, i64 %d, i64 %a
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ret i64 %cond
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}
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define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
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; RV32I-LABEL: cmov_sge_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a3, a5, .LBB9_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: slt a2, a3, a5
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; RV32I-NEXT: xori a2, a2, 1
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; RV32I-NEXT: beqz a2, .LBB9_3
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; RV32I-NEXT: j .LBB9_4
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; RV32I-NEXT: .LBB9_2:
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; RV32I-NEXT: sltu a2, a2, a4
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; RV32I-NEXT: xori a2, a2, 1
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; RV32I-NEXT: bnez a2, .LBB9_4
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; RV32I-NEXT: .LBB9_3:
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; RV32I-NEXT: mv a6, a0
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; RV32I-NEXT: mv a7, a1
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; RV32I-NEXT: .LBB9_4:
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; RV32I-NEXT: mv a0, a6
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; RV32I-NEXT: mv a1, a7
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: cmov_sge_i64:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: beq a3, a5, .LBB9_2
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; RV32IB-NEXT: # %bb.1:
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; RV32IB-NEXT: slt a2, a3, a5
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; RV32IB-NEXT: xori a2, a2, 1
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; RV32IB-NEXT: beqz a2, .LBB9_3
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; RV32IB-NEXT: j .LBB9_4
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; RV32IB-NEXT: .LBB9_2:
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; RV32IB-NEXT: sltu a2, a2, a4
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; RV32IB-NEXT: xori a2, a2, 1
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; RV32IB-NEXT: bnez a2, .LBB9_4
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; RV32IB-NEXT: .LBB9_3:
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; RV32IB-NEXT: mv a6, a0
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; RV32IB-NEXT: mv a7, a1
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; RV32IB-NEXT: .LBB9_4:
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; RV32IB-NEXT: mv a0, a6
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; RV32IB-NEXT: mv a1, a7
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; RV32IB-NEXT: ret
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;
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; RV32IBT-LABEL: cmov_sge_i64:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: beq a3, a5, .LBB9_2
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; RV32IBT-NEXT: # %bb.1:
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; RV32IBT-NEXT: slt a2, a3, a5
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; RV32IBT-NEXT: xori a2, a2, 1
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; RV32IBT-NEXT: beqz a2, .LBB9_3
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; RV32IBT-NEXT: j .LBB9_4
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; RV32IBT-NEXT: .LBB9_2:
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; RV32IBT-NEXT: sltu a2, a2, a4
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; RV32IBT-NEXT: xori a2, a2, 1
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; RV32IBT-NEXT: bnez a2, .LBB9_4
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; RV32IBT-NEXT: .LBB9_3:
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; RV32IBT-NEXT: mv a6, a0
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; RV32IBT-NEXT: mv a7, a1
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; RV32IBT-NEXT: .LBB9_4:
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; RV32IBT-NEXT: mv a0, a6
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; RV32IBT-NEXT: mv a1, a7
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; RV32IBT-NEXT: ret
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%tobool = icmp sge i64 %b, %c
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%cond = select i1 %tobool, i64 %d, i64 %a
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ret i64 %cond
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}
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define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
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; RV32I-LABEL: cmov_ule_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a3, a5, .LBB10_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a2, a5, a3
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; RV32I-NEXT: xori a2, a2, 1
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; RV32I-NEXT: beqz a2, .LBB10_3
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; RV32I-NEXT: j .LBB10_4
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; RV32I-NEXT: .LBB10_2:
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; RV32I-NEXT: sltu a2, a4, a2
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; RV32I-NEXT: xori a2, a2, 1
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; RV32I-NEXT: bnez a2, .LBB10_4
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; RV32I-NEXT: .LBB10_3:
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; RV32I-NEXT: mv a6, a0
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; RV32I-NEXT: mv a7, a1
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; RV32I-NEXT: .LBB10_4:
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; RV32I-NEXT: mv a0, a6
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; RV32I-NEXT: mv a1, a7
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; RV32I-NEXT: ret
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;
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; RV32IB-LABEL: cmov_ule_i64:
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; RV32IB: # %bb.0:
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; RV32IB-NEXT: beq a3, a5, .LBB10_2
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; RV32IB-NEXT: # %bb.1:
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; RV32IB-NEXT: sltu a2, a5, a3
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; RV32IB-NEXT: xori a2, a2, 1
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; RV32IB-NEXT: beqz a2, .LBB10_3
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; RV32IB-NEXT: j .LBB10_4
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; RV32IB-NEXT: .LBB10_2:
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; RV32IB-NEXT: sltu a2, a4, a2
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; RV32IB-NEXT: xori a2, a2, 1
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; RV32IB-NEXT: bnez a2, .LBB10_4
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; RV32IB-NEXT: .LBB10_3:
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; RV32IB-NEXT: mv a6, a0
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; RV32IB-NEXT: mv a7, a1
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; RV32IB-NEXT: .LBB10_4:
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; RV32IB-NEXT: mv a0, a6
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; RV32IB-NEXT: mv a1, a7
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; RV32IB-NEXT: ret
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;
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; RV32IBT-LABEL: cmov_ule_i64:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: beq a3, a5, .LBB10_2
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; RV32IBT-NEXT: # %bb.1:
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; RV32IBT-NEXT: sltu a2, a5, a3
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; RV32IBT-NEXT: xori a2, a2, 1
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; RV32IBT-NEXT: beqz a2, .LBB10_3
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; RV32IBT-NEXT: j .LBB10_4
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; RV32IBT-NEXT: .LBB10_2:
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; RV32IBT-NEXT: sltu a2, a4, a2
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; RV32IBT-NEXT: xori a2, a2, 1
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; RV32IBT-NEXT: bnez a2, .LBB10_4
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; RV32IBT-NEXT: .LBB10_3:
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; RV32IBT-NEXT: mv a6, a0
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; RV32IBT-NEXT: mv a7, a1
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; RV32IBT-NEXT: .LBB10_4:
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; RV32IBT-NEXT: mv a0, a6
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; RV32IBT-NEXT: mv a1, a7
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; RV32IBT-NEXT: ret
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%tobool = icmp ule i64 %b, %c
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%cond = select i1 %tobool, i64 %d, i64 %a
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ret i64 %cond
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}
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define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
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; RV32I-LABEL: cmov_uge_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a3, a5, .LBB11_2
|
||||
; RV32I-NEXT: # %bb.1:
|
||||
; RV32I-NEXT: sltu a2, a3, a5
|
||||
; RV32I-NEXT: xori a2, a2, 1
|
||||
; RV32I-NEXT: beqz a2, .LBB11_3
|
||||
; RV32I-NEXT: j .LBB11_4
|
||||
; RV32I-NEXT: .LBB11_2:
|
||||
; RV32I-NEXT: sltu a2, a2, a4
|
||||
; RV32I-NEXT: xori a2, a2, 1
|
||||
; RV32I-NEXT: bnez a2, .LBB11_4
|
||||
; RV32I-NEXT: .LBB11_3:
|
||||
; RV32I-NEXT: mv a6, a0
|
||||
; RV32I-NEXT: mv a7, a1
|
||||
; RV32I-NEXT: .LBB11_4:
|
||||
; RV32I-NEXT: mv a0, a6
|
||||
; RV32I-NEXT: mv a1, a7
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IB-LABEL: cmov_uge_i64:
|
||||
; RV32IB: # %bb.0:
|
||||
; RV32IB-NEXT: beq a3, a5, .LBB11_2
|
||||
; RV32IB-NEXT: # %bb.1:
|
||||
; RV32IB-NEXT: sltu a2, a3, a5
|
||||
; RV32IB-NEXT: xori a2, a2, 1
|
||||
; RV32IB-NEXT: beqz a2, .LBB11_3
|
||||
; RV32IB-NEXT: j .LBB11_4
|
||||
; RV32IB-NEXT: .LBB11_2:
|
||||
; RV32IB-NEXT: sltu a2, a2, a4
|
||||
; RV32IB-NEXT: xori a2, a2, 1
|
||||
; RV32IB-NEXT: bnez a2, .LBB11_4
|
||||
; RV32IB-NEXT: .LBB11_3:
|
||||
; RV32IB-NEXT: mv a6, a0
|
||||
; RV32IB-NEXT: mv a7, a1
|
||||
; RV32IB-NEXT: .LBB11_4:
|
||||
; RV32IB-NEXT: mv a0, a6
|
||||
; RV32IB-NEXT: mv a1, a7
|
||||
; RV32IB-NEXT: ret
|
||||
;
|
||||
; RV32IBT-LABEL: cmov_uge_i64:
|
||||
; RV32IBT: # %bb.0:
|
||||
; RV32IBT-NEXT: beq a3, a5, .LBB11_2
|
||||
; RV32IBT-NEXT: # %bb.1:
|
||||
; RV32IBT-NEXT: sltu a2, a3, a5
|
||||
; RV32IBT-NEXT: xori a2, a2, 1
|
||||
; RV32IBT-NEXT: beqz a2, .LBB11_3
|
||||
; RV32IBT-NEXT: j .LBB11_4
|
||||
; RV32IBT-NEXT: .LBB11_2:
|
||||
; RV32IBT-NEXT: sltu a2, a2, a4
|
||||
; RV32IBT-NEXT: xori a2, a2, 1
|
||||
; RV32IBT-NEXT: bnez a2, .LBB11_4
|
||||
; RV32IBT-NEXT: .LBB11_3:
|
||||
; RV32IBT-NEXT: mv a6, a0
|
||||
; RV32IBT-NEXT: mv a7, a1
|
||||
; RV32IBT-NEXT: .LBB11_4:
|
||||
; RV32IBT-NEXT: mv a0, a6
|
||||
; RV32IBT-NEXT: mv a1, a7
|
||||
; RV32IBT-NEXT: ret
|
||||
%tobool = icmp uge i64 %b, %c
|
||||
%cond = select i1 %tobool, i64 %d, i64 %a
|
||||
ret i64 %cond
|
||||
}
|
||||
|
||||
declare i32 @llvm.fshl.i32(i32, i32, i32)
|
||||
|
||||
define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind {
|
||||
|
|
@ -158,26 +546,26 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32I-NEXT: andi a5, a4, 63
|
||||
; RV32I-NEXT: addi t1, a5, -32
|
||||
; RV32I-NEXT: addi a6, zero, 31
|
||||
; RV32I-NEXT: bltz t1, .LBB5_2
|
||||
; RV32I-NEXT: bltz t1, .LBB13_2
|
||||
; RV32I-NEXT: # %bb.1:
|
||||
; RV32I-NEXT: sll a7, a0, t1
|
||||
; RV32I-NEXT: j .LBB5_3
|
||||
; RV32I-NEXT: .LBB5_2:
|
||||
; RV32I-NEXT: j .LBB13_3
|
||||
; RV32I-NEXT: .LBB13_2:
|
||||
; RV32I-NEXT: sll a7, a1, a4
|
||||
; RV32I-NEXT: sub a5, a6, a5
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: srl a1, a1, a5
|
||||
; RV32I-NEXT: or a7, a7, a1
|
||||
; RV32I-NEXT: .LBB5_3:
|
||||
; RV32I-NEXT: .LBB13_3:
|
||||
; RV32I-NEXT: not a1, a4
|
||||
; RV32I-NEXT: andi t3, a1, 63
|
||||
; RV32I-NEXT: addi a5, t3, -32
|
||||
; RV32I-NEXT: srli t2, a3, 1
|
||||
; RV32I-NEXT: bltz a5, .LBB5_7
|
||||
; RV32I-NEXT: bltz a5, .LBB13_7
|
||||
; RV32I-NEXT: # %bb.4:
|
||||
; RV32I-NEXT: mv t0, zero
|
||||
; RV32I-NEXT: bgez a5, .LBB5_8
|
||||
; RV32I-NEXT: .LBB5_5:
|
||||
; RV32I-NEXT: bgez a5, .LBB13_8
|
||||
; RV32I-NEXT: .LBB13_5:
|
||||
; RV32I-NEXT: slli a3, a3, 31
|
||||
; RV32I-NEXT: srli a2, a2, 1
|
||||
; RV32I-NEXT: or a2, a2, a3
|
||||
|
|
@ -187,19 +575,19 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32I-NEXT: sll a2, a3, a2
|
||||
; RV32I-NEXT: or a2, a1, a2
|
||||
; RV32I-NEXT: or a1, a7, t0
|
||||
; RV32I-NEXT: bgez t1, .LBB5_9
|
||||
; RV32I-NEXT: .LBB5_6:
|
||||
; RV32I-NEXT: bgez t1, .LBB13_9
|
||||
; RV32I-NEXT: .LBB13_6:
|
||||
; RV32I-NEXT: sll a0, a0, a4
|
||||
; RV32I-NEXT: or a0, a0, a2
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: .LBB5_7:
|
||||
; RV32I-NEXT: .LBB13_7:
|
||||
; RV32I-NEXT: srl t0, t2, a1
|
||||
; RV32I-NEXT: bltz a5, .LBB5_5
|
||||
; RV32I-NEXT: .LBB5_8:
|
||||
; RV32I-NEXT: bltz a5, .LBB13_5
|
||||
; RV32I-NEXT: .LBB13_8:
|
||||
; RV32I-NEXT: srl a2, t2, a5
|
||||
; RV32I-NEXT: or a1, a7, t0
|
||||
; RV32I-NEXT: bltz t1, .LBB5_6
|
||||
; RV32I-NEXT: .LBB5_9:
|
||||
; RV32I-NEXT: bltz t1, .LBB13_6
|
||||
; RV32I-NEXT: .LBB13_9:
|
||||
; RV32I-NEXT: or a0, zero, a2
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
|
|
@ -208,27 +596,27 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IB-NEXT: andi a5, a4, 63
|
||||
; RV32IB-NEXT: addi t2, a5, -32
|
||||
; RV32IB-NEXT: addi a6, zero, 31
|
||||
; RV32IB-NEXT: bltz t2, .LBB5_2
|
||||
; RV32IB-NEXT: bltz t2, .LBB13_2
|
||||
; RV32IB-NEXT: # %bb.1:
|
||||
; RV32IB-NEXT: sll a7, a0, t2
|
||||
; RV32IB-NEXT: j .LBB5_3
|
||||
; RV32IB-NEXT: .LBB5_2:
|
||||
; RV32IB-NEXT: j .LBB13_3
|
||||
; RV32IB-NEXT: .LBB13_2:
|
||||
; RV32IB-NEXT: sll a7, a1, a4
|
||||
; RV32IB-NEXT: sub a5, a6, a5
|
||||
; RV32IB-NEXT: srli a1, a0, 1
|
||||
; RV32IB-NEXT: srl a1, a1, a5
|
||||
; RV32IB-NEXT: or a7, a7, a1
|
||||
; RV32IB-NEXT: .LBB5_3:
|
||||
; RV32IB-NEXT: .LBB13_3:
|
||||
; RV32IB-NEXT: not t1, a4
|
||||
; RV32IB-NEXT: addi a1, zero, 63
|
||||
; RV32IB-NEXT: andn a5, a1, a4
|
||||
; RV32IB-NEXT: addi a1, a5, -32
|
||||
; RV32IB-NEXT: srli t3, a3, 1
|
||||
; RV32IB-NEXT: bltz a1, .LBB5_7
|
||||
; RV32IB-NEXT: bltz a1, .LBB13_7
|
||||
; RV32IB-NEXT: # %bb.4:
|
||||
; RV32IB-NEXT: mv t0, zero
|
||||
; RV32IB-NEXT: bgez a1, .LBB5_8
|
||||
; RV32IB-NEXT: .LBB5_5:
|
||||
; RV32IB-NEXT: bgez a1, .LBB13_8
|
||||
; RV32IB-NEXT: .LBB13_5:
|
||||
; RV32IB-NEXT: fsri a1, a2, a3, 1
|
||||
; RV32IB-NEXT: srl a1, a1, t1
|
||||
; RV32IB-NEXT: sub a2, a6, a5
|
||||
|
|
@ -236,19 +624,19 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IB-NEXT: sll a2, a3, a2
|
||||
; RV32IB-NEXT: or a2, a1, a2
|
||||
; RV32IB-NEXT: or a1, a7, t0
|
||||
; RV32IB-NEXT: bgez t2, .LBB5_9
|
||||
; RV32IB-NEXT: .LBB5_6:
|
||||
; RV32IB-NEXT: bgez t2, .LBB13_9
|
||||
; RV32IB-NEXT: .LBB13_6:
|
||||
; RV32IB-NEXT: sll a0, a0, a4
|
||||
; RV32IB-NEXT: or a0, a0, a2
|
||||
; RV32IB-NEXT: ret
|
||||
; RV32IB-NEXT: .LBB5_7:
|
||||
; RV32IB-NEXT: .LBB13_7:
|
||||
; RV32IB-NEXT: srl t0, t3, t1
|
||||
; RV32IB-NEXT: bltz a1, .LBB5_5
|
||||
; RV32IB-NEXT: .LBB5_8:
|
||||
; RV32IB-NEXT: bltz a1, .LBB13_5
|
||||
; RV32IB-NEXT: .LBB13_8:
|
||||
; RV32IB-NEXT: srl a2, t3, a1
|
||||
; RV32IB-NEXT: or a1, a7, t0
|
||||
; RV32IB-NEXT: bltz t2, .LBB5_6
|
||||
; RV32IB-NEXT: .LBB5_9:
|
||||
; RV32IB-NEXT: bltz t2, .LBB13_6
|
||||
; RV32IB-NEXT: .LBB13_9:
|
||||
; RV32IB-NEXT: or a0, zero, a2
|
||||
; RV32IB-NEXT: ret
|
||||
;
|
||||
|
|
@ -257,26 +645,26 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IBT-NEXT: andi a5, a4, 63
|
||||
; RV32IBT-NEXT: addi t1, a5, -32
|
||||
; RV32IBT-NEXT: addi a6, zero, 31
|
||||
; RV32IBT-NEXT: bltz t1, .LBB5_2
|
||||
; RV32IBT-NEXT: bltz t1, .LBB13_2
|
||||
; RV32IBT-NEXT: # %bb.1:
|
||||
; RV32IBT-NEXT: sll a7, a0, t1
|
||||
; RV32IBT-NEXT: j .LBB5_3
|
||||
; RV32IBT-NEXT: .LBB5_2:
|
||||
; RV32IBT-NEXT: j .LBB13_3
|
||||
; RV32IBT-NEXT: .LBB13_2:
|
||||
; RV32IBT-NEXT: sll a7, a1, a4
|
||||
; RV32IBT-NEXT: sub a5, a6, a5
|
||||
; RV32IBT-NEXT: srli a1, a0, 1
|
||||
; RV32IBT-NEXT: srl a1, a1, a5
|
||||
; RV32IBT-NEXT: or a7, a7, a1
|
||||
; RV32IBT-NEXT: .LBB5_3:
|
||||
; RV32IBT-NEXT: .LBB13_3:
|
||||
; RV32IBT-NEXT: not a1, a4
|
||||
; RV32IBT-NEXT: andi t3, a1, 63
|
||||
; RV32IBT-NEXT: addi a5, t3, -32
|
||||
; RV32IBT-NEXT: srli t2, a3, 1
|
||||
; RV32IBT-NEXT: bltz a5, .LBB5_7
|
||||
; RV32IBT-NEXT: bltz a5, .LBB13_7
|
||||
; RV32IBT-NEXT: # %bb.4:
|
||||
; RV32IBT-NEXT: mv t0, zero
|
||||
; RV32IBT-NEXT: bgez a5, .LBB5_8
|
||||
; RV32IBT-NEXT: .LBB5_5:
|
||||
; RV32IBT-NEXT: bgez a5, .LBB13_8
|
||||
; RV32IBT-NEXT: .LBB13_5:
|
||||
; RV32IBT-NEXT: fsri a2, a2, a3, 1
|
||||
; RV32IBT-NEXT: srl a1, a2, a1
|
||||
; RV32IBT-NEXT: sub a2, a6, t3
|
||||
|
|
@ -284,19 +672,19 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IBT-NEXT: sll a2, a3, a2
|
||||
; RV32IBT-NEXT: or a2, a1, a2
|
||||
; RV32IBT-NEXT: or a1, a7, t0
|
||||
; RV32IBT-NEXT: bgez t1, .LBB5_9
|
||||
; RV32IBT-NEXT: .LBB5_6:
|
||||
; RV32IBT-NEXT: bgez t1, .LBB13_9
|
||||
; RV32IBT-NEXT: .LBB13_6:
|
||||
; RV32IBT-NEXT: sll a0, a0, a4
|
||||
; RV32IBT-NEXT: or a0, a0, a2
|
||||
; RV32IBT-NEXT: ret
|
||||
; RV32IBT-NEXT: .LBB5_7:
|
||||
; RV32IBT-NEXT: .LBB13_7:
|
||||
; RV32IBT-NEXT: srl t0, t2, a1
|
||||
; RV32IBT-NEXT: bltz a5, .LBB5_5
|
||||
; RV32IBT-NEXT: .LBB5_8:
|
||||
; RV32IBT-NEXT: bltz a5, .LBB13_5
|
||||
; RV32IBT-NEXT: .LBB13_8:
|
||||
; RV32IBT-NEXT: srl a2, t2, a5
|
||||
; RV32IBT-NEXT: or a1, a7, t0
|
||||
; RV32IBT-NEXT: bltz t1, .LBB5_6
|
||||
; RV32IBT-NEXT: .LBB5_9:
|
||||
; RV32IBT-NEXT: bltz t1, .LBB13_6
|
||||
; RV32IBT-NEXT: .LBB13_9:
|
||||
; RV32IBT-NEXT: or a0, zero, a2
|
||||
; RV32IBT-NEXT: ret
|
||||
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c)
|
||||
|
|
@ -344,26 +732,26 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32I-NEXT: andi a5, a4, 63
|
||||
; RV32I-NEXT: addi t1, a5, -32
|
||||
; RV32I-NEXT: addi a6, zero, 31
|
||||
; RV32I-NEXT: bltz t1, .LBB7_2
|
||||
; RV32I-NEXT: bltz t1, .LBB15_2
|
||||
; RV32I-NEXT: # %bb.1:
|
||||
; RV32I-NEXT: srl a7, a3, t1
|
||||
; RV32I-NEXT: j .LBB7_3
|
||||
; RV32I-NEXT: .LBB7_2:
|
||||
; RV32I-NEXT: j .LBB15_3
|
||||
; RV32I-NEXT: .LBB15_2:
|
||||
; RV32I-NEXT: srl a7, a2, a4
|
||||
; RV32I-NEXT: sub a5, a6, a5
|
||||
; RV32I-NEXT: slli a2, a3, 1
|
||||
; RV32I-NEXT: sll a2, a2, a5
|
||||
; RV32I-NEXT: or a7, a7, a2
|
||||
; RV32I-NEXT: .LBB7_3:
|
||||
; RV32I-NEXT: .LBB15_3:
|
||||
; RV32I-NEXT: not a2, a4
|
||||
; RV32I-NEXT: andi t2, a2, 63
|
||||
; RV32I-NEXT: addi a5, t2, -32
|
||||
; RV32I-NEXT: slli t3, a0, 1
|
||||
; RV32I-NEXT: bltz a5, .LBB7_7
|
||||
; RV32I-NEXT: bltz a5, .LBB15_7
|
||||
; RV32I-NEXT: # %bb.4:
|
||||
; RV32I-NEXT: mv t0, zero
|
||||
; RV32I-NEXT: bgez a5, .LBB7_8
|
||||
; RV32I-NEXT: .LBB7_5:
|
||||
; RV32I-NEXT: bgez a5, .LBB15_8
|
||||
; RV32I-NEXT: .LBB15_5:
|
||||
; RV32I-NEXT: lui a5, 524288
|
||||
; RV32I-NEXT: addi a5, a5, -1
|
||||
; RV32I-NEXT: and t3, a0, a5
|
||||
|
|
@ -375,19 +763,19 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32I-NEXT: sll a0, a0, a2
|
||||
; RV32I-NEXT: or a1, a0, a5
|
||||
; RV32I-NEXT: or a0, t0, a7
|
||||
; RV32I-NEXT: bgez t1, .LBB7_9
|
||||
; RV32I-NEXT: .LBB7_6:
|
||||
; RV32I-NEXT: bgez t1, .LBB15_9
|
||||
; RV32I-NEXT: .LBB15_6:
|
||||
; RV32I-NEXT: srl a2, a3, a4
|
||||
; RV32I-NEXT: or a1, a1, a2
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: .LBB7_7:
|
||||
; RV32I-NEXT: .LBB15_7:
|
||||
; RV32I-NEXT: sll t0, t3, a2
|
||||
; RV32I-NEXT: bltz a5, .LBB7_5
|
||||
; RV32I-NEXT: .LBB7_8:
|
||||
; RV32I-NEXT: bltz a5, .LBB15_5
|
||||
; RV32I-NEXT: .LBB15_8:
|
||||
; RV32I-NEXT: sll a1, t3, a5
|
||||
; RV32I-NEXT: or a0, t0, a7
|
||||
; RV32I-NEXT: bltz t1, .LBB7_6
|
||||
; RV32I-NEXT: .LBB7_9:
|
||||
; RV32I-NEXT: bltz t1, .LBB15_6
|
||||
; RV32I-NEXT: .LBB15_9:
|
||||
; RV32I-NEXT: or a1, a1, zero
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
|
|
@ -396,27 +784,27 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IB-NEXT: andi a5, a4, 63
|
||||
; RV32IB-NEXT: addi t2, a5, -32
|
||||
; RV32IB-NEXT: addi a6, zero, 31
|
||||
; RV32IB-NEXT: bltz t2, .LBB7_2
|
||||
; RV32IB-NEXT: bltz t2, .LBB15_2
|
||||
; RV32IB-NEXT: # %bb.1:
|
||||
; RV32IB-NEXT: srl a7, a3, t2
|
||||
; RV32IB-NEXT: j .LBB7_3
|
||||
; RV32IB-NEXT: .LBB7_2:
|
||||
; RV32IB-NEXT: j .LBB15_3
|
||||
; RV32IB-NEXT: .LBB15_2:
|
||||
; RV32IB-NEXT: srl a7, a2, a4
|
||||
; RV32IB-NEXT: sub a5, a6, a5
|
||||
; RV32IB-NEXT: slli a2, a3, 1
|
||||
; RV32IB-NEXT: sll a2, a2, a5
|
||||
; RV32IB-NEXT: or a7, a7, a2
|
||||
; RV32IB-NEXT: .LBB7_3:
|
||||
; RV32IB-NEXT: .LBB15_3:
|
||||
; RV32IB-NEXT: not t1, a4
|
||||
; RV32IB-NEXT: addi a2, zero, 63
|
||||
; RV32IB-NEXT: andn a2, a2, a4
|
||||
; RV32IB-NEXT: addi a5, a2, -32
|
||||
; RV32IB-NEXT: slli t3, a0, 1
|
||||
; RV32IB-NEXT: bltz a5, .LBB7_7
|
||||
; RV32IB-NEXT: bltz a5, .LBB15_7
|
||||
; RV32IB-NEXT: # %bb.4:
|
||||
; RV32IB-NEXT: mv t0, zero
|
||||
; RV32IB-NEXT: bgez a5, .LBB7_8
|
||||
; RV32IB-NEXT: .LBB7_5:
|
||||
; RV32IB-NEXT: bgez a5, .LBB15_8
|
||||
; RV32IB-NEXT: .LBB15_5:
|
||||
; RV32IB-NEXT: fsri a1, a0, a1, 31
|
||||
; RV32IB-NEXT: sll a1, a1, t1
|
||||
; RV32IB-NEXT: sub a2, a6, a2
|
||||
|
|
@ -424,19 +812,19 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IB-NEXT: srl a0, a0, a2
|
||||
; RV32IB-NEXT: or a1, a1, a0
|
||||
; RV32IB-NEXT: or a0, t0, a7
|
||||
; RV32IB-NEXT: bgez t2, .LBB7_9
|
||||
; RV32IB-NEXT: .LBB7_6:
|
||||
; RV32IB-NEXT: bgez t2, .LBB15_9
|
||||
; RV32IB-NEXT: .LBB15_6:
|
||||
; RV32IB-NEXT: srl a2, a3, a4
|
||||
; RV32IB-NEXT: or a1, a1, a2
|
||||
; RV32IB-NEXT: ret
|
||||
; RV32IB-NEXT: .LBB7_7:
|
||||
; RV32IB-NEXT: .LBB15_7:
|
||||
; RV32IB-NEXT: sll t0, t3, t1
|
||||
; RV32IB-NEXT: bltz a5, .LBB7_5
|
||||
; RV32IB-NEXT: .LBB7_8:
|
||||
; RV32IB-NEXT: bltz a5, .LBB15_5
|
||||
; RV32IB-NEXT: .LBB15_8:
|
||||
; RV32IB-NEXT: sll a1, t3, a5
|
||||
; RV32IB-NEXT: or a0, t0, a7
|
||||
; RV32IB-NEXT: bltz t2, .LBB7_6
|
||||
; RV32IB-NEXT: .LBB7_9:
|
||||
; RV32IB-NEXT: bltz t2, .LBB15_6
|
||||
; RV32IB-NEXT: .LBB15_9:
|
||||
; RV32IB-NEXT: or a1, a1, zero
|
||||
; RV32IB-NEXT: ret
|
||||
;
|
||||
|
|
@ -445,26 +833,26 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IBT-NEXT: andi a5, a4, 63
|
||||
; RV32IBT-NEXT: addi t1, a5, -32
|
||||
; RV32IBT-NEXT: addi a6, zero, 31
|
||||
; RV32IBT-NEXT: bltz t1, .LBB7_2
|
||||
; RV32IBT-NEXT: bltz t1, .LBB15_2
|
||||
; RV32IBT-NEXT: # %bb.1:
|
||||
; RV32IBT-NEXT: srl a7, a3, t1
|
||||
; RV32IBT-NEXT: j .LBB7_3
|
||||
; RV32IBT-NEXT: .LBB7_2:
|
||||
; RV32IBT-NEXT: j .LBB15_3
|
||||
; RV32IBT-NEXT: .LBB15_2:
|
||||
; RV32IBT-NEXT: srl a7, a2, a4
|
||||
; RV32IBT-NEXT: sub a5, a6, a5
|
||||
; RV32IBT-NEXT: slli a2, a3, 1
|
||||
; RV32IBT-NEXT: sll a2, a2, a5
|
||||
; RV32IBT-NEXT: or a7, a7, a2
|
||||
; RV32IBT-NEXT: .LBB7_3:
|
||||
; RV32IBT-NEXT: .LBB15_3:
|
||||
; RV32IBT-NEXT: not a2, a4
|
||||
; RV32IBT-NEXT: andi t2, a2, 63
|
||||
; RV32IBT-NEXT: addi a5, t2, -32
|
||||
; RV32IBT-NEXT: slli t3, a0, 1
|
||||
; RV32IBT-NEXT: bltz a5, .LBB7_7
|
||||
; RV32IBT-NEXT: bltz a5, .LBB15_7
|
||||
; RV32IBT-NEXT: # %bb.4:
|
||||
; RV32IBT-NEXT: mv t0, zero
|
||||
; RV32IBT-NEXT: bgez a5, .LBB7_8
|
||||
; RV32IBT-NEXT: .LBB7_5:
|
||||
; RV32IBT-NEXT: bgez a5, .LBB15_8
|
||||
; RV32IBT-NEXT: .LBB15_5:
|
||||
; RV32IBT-NEXT: lui a5, 524288
|
||||
; RV32IBT-NEXT: addi a5, a5, -1
|
||||
; RV32IBT-NEXT: and t3, a0, a5
|
||||
|
|
@ -474,19 +862,19 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
; RV32IBT-NEXT: sll a0, a0, a2
|
||||
; RV32IBT-NEXT: or a1, a0, a5
|
||||
; RV32IBT-NEXT: or a0, t0, a7
|
||||
; RV32IBT-NEXT: bgez t1, .LBB7_9
|
||||
; RV32IBT-NEXT: .LBB7_6:
|
||||
; RV32IBT-NEXT: bgez t1, .LBB15_9
|
||||
; RV32IBT-NEXT: .LBB15_6:
|
||||
; RV32IBT-NEXT: srl a2, a3, a4
|
||||
; RV32IBT-NEXT: or a1, a1, a2
|
||||
; RV32IBT-NEXT: ret
|
||||
; RV32IBT-NEXT: .LBB7_7:
|
||||
; RV32IBT-NEXT: .LBB15_7:
|
||||
; RV32IBT-NEXT: sll t0, t3, a2
|
||||
; RV32IBT-NEXT: bltz a5, .LBB7_5
|
||||
; RV32IBT-NEXT: .LBB7_8:
|
||||
; RV32IBT-NEXT: bltz a5, .LBB15_5
|
||||
; RV32IBT-NEXT: .LBB15_8:
|
||||
; RV32IBT-NEXT: sll a1, t3, a5
|
||||
; RV32IBT-NEXT: or a0, t0, a7
|
||||
; RV32IBT-NEXT: bltz t1, .LBB7_6
|
||||
; RV32IBT-NEXT: .LBB7_9:
|
||||
; RV32IBT-NEXT: bltz t1, .LBB15_6
|
||||
; RV32IBT-NEXT: .LBB15_9:
|
||||
; RV32IBT-NEXT: or a1, a1, zero
|
||||
; RV32IBT-NEXT: ret
|
||||
%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
|
||||
|
|
|
|||
|
|
@ -80,13 +80,141 @@ define signext i32 @cmov_i32(i32 signext %a, i32 signext %b, i32 signext %c) nou
|
|||
ret i32 %cond
|
||||
}
|
||||
|
||||
define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
|
||||
; RV64I-LABEL: cmov_sle_i32:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bge a2, a1, .LBB3_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB3_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_sle_i32:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bge a2, a1, .LBB3_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB3_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_sle_i32:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bge a2, a1, .LBB3_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB3_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp sle i32 %b, %c
|
||||
%cond = select i1 %tobool, i32 %d, i32 %a
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
|
||||
; RV64I-LABEL: cmov_sge_i32:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bge a1, a2, .LBB4_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB4_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_sge_i32:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bge a1, a2, .LBB4_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB4_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_sge_i32:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bge a1, a2, .LBB4_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB4_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp sge i32 %b, %c
|
||||
%cond = select i1 %tobool, i32 %d, i32 %a
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
|
||||
; RV64I-LABEL: cmov_ule_i32:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bgeu a2, a1, .LBB5_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB5_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_ule_i32:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bgeu a2, a1, .LBB5_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB5_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_ule_i32:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bgeu a2, a1, .LBB5_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB5_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp ule i32 %b, %c
|
||||
%cond = select i1 %tobool, i32 %d, i32 %a
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
|
||||
; RV64I-LABEL: cmov_uge_i32:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bgeu a1, a2, .LBB6_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB6_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_uge_i32:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bgeu a1, a2, .LBB6_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB6_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_uge_i32:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bgeu a1, a2, .LBB6_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB6_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp uge i32 %b, %c
|
||||
%cond = select i1 %tobool, i32 %d, i32 %a
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
||||
; RV64I-LABEL: cmov_i64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: beqz a1, .LBB3_2
|
||||
; RV64I-NEXT: beqz a1, .LBB7_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a2, a0
|
||||
; RV64I-NEXT: .LBB3_2:
|
||||
; RV64I-NEXT: .LBB7_2:
|
||||
; RV64I-NEXT: mv a0, a2
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
|
|
@ -104,6 +232,134 @@ define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
|
|||
ret i64 %cond
|
||||
}
|
||||
|
||||
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
|
||||
; RV64I-LABEL: cmov_sle_i64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bge a2, a1, .LBB8_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB8_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_sle_i64:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bge a2, a1, .LBB8_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB8_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_sle_i64:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bge a2, a1, .LBB8_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB8_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp sle i64 %b, %c
|
||||
%cond = select i1 %tobool, i64 %d, i64 %a
|
||||
ret i64 %cond
|
||||
}
|
||||
|
||||
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
|
||||
; RV64I-LABEL: cmov_sge_i64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bge a1, a2, .LBB9_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB9_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_sge_i64:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bge a1, a2, .LBB9_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB9_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_sge_i64:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bge a1, a2, .LBB9_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB9_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp sge i64 %b, %c
|
||||
%cond = select i1 %tobool, i64 %d, i64 %a
|
||||
ret i64 %cond
|
||||
}
|
||||
|
||||
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
|
||||
; RV64I-LABEL: cmov_ule_i64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bgeu a2, a1, .LBB10_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB10_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_ule_i64:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bgeu a2, a1, .LBB10_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB10_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_ule_i64:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bgeu a2, a1, .LBB10_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB10_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp ule i64 %b, %c
|
||||
%cond = select i1 %tobool, i64 %d, i64 %a
|
||||
ret i64 %cond
|
||||
}
|
||||
|
||||
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
|
||||
; RV64I-LABEL: cmov_uge_i64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: bgeu a1, a2, .LBB11_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: mv a3, a0
|
||||
; RV64I-NEXT: .LBB11_2:
|
||||
; RV64I-NEXT: mv a0, a3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IB-LABEL: cmov_uge_i64:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bgeu a1, a2, .LBB11_2
|
||||
; RV64IB-NEXT: # %bb.1:
|
||||
; RV64IB-NEXT: mv a3, a0
|
||||
; RV64IB-NEXT: .LBB11_2:
|
||||
; RV64IB-NEXT: mv a0, a3
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBT-LABEL: cmov_uge_i64:
|
||||
; RV64IBT: # %bb.0:
|
||||
; RV64IBT-NEXT: bgeu a1, a2, .LBB11_2
|
||||
; RV64IBT-NEXT: # %bb.1:
|
||||
; RV64IBT-NEXT: mv a3, a0
|
||||
; RV64IBT-NEXT: .LBB11_2:
|
||||
; RV64IBT-NEXT: mv a0, a3
|
||||
; RV64IBT-NEXT: ret
|
||||
%tobool = icmp uge i64 %b, %c
|
||||
%cond = select i1 %tobool, i64 %d, i64 %a
|
||||
ret i64 %cond
|
||||
}
|
||||
|
||||
declare i32 @llvm.fshl.i32(i32, i32, i32)
|
||||
|
||||
define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
|
||||
|
|
|
|||
Loading…
Reference in New Issue