forked from OSchip/llvm-project
[ELF] Move updateARMVFPArgs/updateARMVFPArgs. NFC
To reduce diff for D130810.
This commit is contained in:
Fangrui Song
parent
91e8079cd5
commit
e2a932dd8a
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@ -89,6 +89,92 @@ static ELFKind getELFKind(MemoryBufferRef mb, StringRef archiveName) {
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return (endian == ELFDATA2LSB) ? ELF64LEKind : ELF64BEKind;
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}
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// For ARM only, to set the EF_ARM_ABI_FLOAT_SOFT or EF_ARM_ABI_FLOAT_HARD
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// flag in the ELF Header we need to look at Tag_ABI_VFP_args to find out how
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// the input objects have been compiled.
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static void updateARMVFPArgs(const ARMAttributeParser &attributes,
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const InputFile *f) {
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Optional<unsigned> attr =
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attributes.getAttributeValue(ARMBuildAttrs::ABI_VFP_args);
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if (!attr)
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// If an ABI tag isn't present then it is implicitly given the value of 0
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// which maps to ARMBuildAttrs::BaseAAPCS. However many assembler files,
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// including some in glibc that don't use FP args (and should have value 3)
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// don't have the attribute so we do not consider an implicit value of 0
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// as a clash.
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return;
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unsigned vfpArgs = *attr;
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ARMVFPArgKind arg;
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switch (vfpArgs) {
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case ARMBuildAttrs::BaseAAPCS:
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arg = ARMVFPArgKind::Base;
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break;
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case ARMBuildAttrs::HardFPAAPCS:
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arg = ARMVFPArgKind::VFP;
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break;
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case ARMBuildAttrs::ToolChainFPPCS:
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// Tool chain specific convention that conforms to neither AAPCS variant.
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arg = ARMVFPArgKind::ToolChain;
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break;
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case ARMBuildAttrs::CompatibleFPAAPCS:
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// Object compatible with all conventions.
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return;
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default:
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error(toString(f) + ": unknown Tag_ABI_VFP_args value: " + Twine(vfpArgs));
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return;
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}
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// Follow ld.bfd and error if there is a mix of calling conventions.
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if (config->armVFPArgs != arg && config->armVFPArgs != ARMVFPArgKind::Default)
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error(toString(f) + ": incompatible Tag_ABI_VFP_args");
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else
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config->armVFPArgs = arg;
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}
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// The ARM support in lld makes some use of instructions that are not available
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// on all ARM architectures. Namely:
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// - Use of BLX instruction for interworking between ARM and Thumb state.
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// - Use of the extended Thumb branch encoding in relocation.
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// - Use of the MOVT/MOVW instructions in Thumb Thunks.
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// The ARM Attributes section contains information about the architecture chosen
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// at compile time. We follow the convention that if at least one input object
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// is compiled with an architecture that supports these features then lld is
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// permitted to use them.
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static void updateSupportedARMFeatures(const ARMAttributeParser &attributes) {
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Optional<unsigned> attr =
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attributes.getAttributeValue(ARMBuildAttrs::CPU_arch);
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if (!attr)
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return;
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auto arch = attr.value();
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switch (arch) {
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case ARMBuildAttrs::Pre_v4:
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case ARMBuildAttrs::v4:
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case ARMBuildAttrs::v4T:
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// Architectures prior to v5 do not support BLX instruction
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break;
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case ARMBuildAttrs::v5T:
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case ARMBuildAttrs::v5TE:
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case ARMBuildAttrs::v5TEJ:
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case ARMBuildAttrs::v6:
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case ARMBuildAttrs::v6KZ:
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case ARMBuildAttrs::v6K:
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config->armHasBlx = true;
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// Architectures used in pre-Cortex processors do not support
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// The J1 = 1 J2 = 1 Thumb branch range extension, with the exception
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// of Architecture v6T2 (arm1156t2-s and arm1156t2f-s) that do.
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break;
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default:
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// All other Architectures have BLX and extended branch encoding
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config->armHasBlx = true;
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config->armJ1J2BranchEncoding = true;
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if (arch != ARMBuildAttrs::v6_M && arch != ARMBuildAttrs::v6S_M)
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// All Architectures used in Cortex processors with the exception
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// of v6-M and v6S-M have the MOVT and MOVW instructions.
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config->armHasMovtMovw = true;
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break;
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}
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}
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InputFile::InputFile(Kind k, MemoryBufferRef m)
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: mb(m), groupId(nextGroupId), fileKind(k) {
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// All files within the same --{start,end}-group get the same group ID.
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@ -683,92 +769,6 @@ void ObjFile<ELFT>::initializeSections(bool ignoreComdats,
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handleSectionGroup<ELFT>(this->sections, entries);
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}
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// For ARM only, to set the EF_ARM_ABI_FLOAT_SOFT or EF_ARM_ABI_FLOAT_HARD
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// flag in the ELF Header we need to look at Tag_ABI_VFP_args to find out how
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// the input objects have been compiled.
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static void updateARMVFPArgs(const ARMAttributeParser &attributes,
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const InputFile *f) {
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Optional<unsigned> attr =
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attributes.getAttributeValue(ARMBuildAttrs::ABI_VFP_args);
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if (!attr)
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// If an ABI tag isn't present then it is implicitly given the value of 0
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// which maps to ARMBuildAttrs::BaseAAPCS. However many assembler files,
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// including some in glibc that don't use FP args (and should have value 3)
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// don't have the attribute so we do not consider an implicit value of 0
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// as a clash.
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return;
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unsigned vfpArgs = *attr;
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ARMVFPArgKind arg;
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switch (vfpArgs) {
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case ARMBuildAttrs::BaseAAPCS:
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arg = ARMVFPArgKind::Base;
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break;
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case ARMBuildAttrs::HardFPAAPCS:
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arg = ARMVFPArgKind::VFP;
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break;
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case ARMBuildAttrs::ToolChainFPPCS:
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// Tool chain specific convention that conforms to neither AAPCS variant.
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arg = ARMVFPArgKind::ToolChain;
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break;
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case ARMBuildAttrs::CompatibleFPAAPCS:
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// Object compatible with all conventions.
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return;
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default:
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error(toString(f) + ": unknown Tag_ABI_VFP_args value: " + Twine(vfpArgs));
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return;
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}
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// Follow ld.bfd and error if there is a mix of calling conventions.
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if (config->armVFPArgs != arg && config->armVFPArgs != ARMVFPArgKind::Default)
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error(toString(f) + ": incompatible Tag_ABI_VFP_args");
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else
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config->armVFPArgs = arg;
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}
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// The ARM support in lld makes some use of instructions that are not available
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// on all ARM architectures. Namely:
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// - Use of BLX instruction for interworking between ARM and Thumb state.
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// - Use of the extended Thumb branch encoding in relocation.
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// - Use of the MOVT/MOVW instructions in Thumb Thunks.
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// The ARM Attributes section contains information about the architecture chosen
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// at compile time. We follow the convention that if at least one input object
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// is compiled with an architecture that supports these features then lld is
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// permitted to use them.
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static void updateSupportedARMFeatures(const ARMAttributeParser &attributes) {
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Optional<unsigned> attr =
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attributes.getAttributeValue(ARMBuildAttrs::CPU_arch);
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if (!attr)
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return;
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auto arch = attr.value();
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switch (arch) {
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case ARMBuildAttrs::Pre_v4:
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case ARMBuildAttrs::v4:
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case ARMBuildAttrs::v4T:
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// Architectures prior to v5 do not support BLX instruction
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break;
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case ARMBuildAttrs::v5T:
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case ARMBuildAttrs::v5TE:
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case ARMBuildAttrs::v5TEJ:
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case ARMBuildAttrs::v6:
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case ARMBuildAttrs::v6KZ:
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case ARMBuildAttrs::v6K:
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config->armHasBlx = true;
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// Architectures used in pre-Cortex processors do not support
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// The J1 = 1 J2 = 1 Thumb branch range extension, with the exception
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// of Architecture v6T2 (arm1156t2-s and arm1156t2f-s) that do.
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break;
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default:
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// All other Architectures have BLX and extended branch encoding
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config->armHasBlx = true;
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config->armJ1J2BranchEncoding = true;
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if (arch != ARMBuildAttrs::v6_M && arch != ARMBuildAttrs::v6S_M)
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// All Architectures used in Cortex processors with the exception
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// of v6-M and v6S-M have the MOVT and MOVW instructions.
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config->armHasMovtMovw = true;
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break;
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}
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}
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// If a source file is compiled with x86 hardware-assisted call flow control
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// enabled, the generated object file contains feature flags indicating that
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// fact. This function reads the feature flags and returns it.
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