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[AMDGPU] Remove double map lookups in SI scheduler 

Patch by Axel Davy (axel.davy@normalesup.org)

Differential revision: https://reviews.llvm.org/D30382

llvm-svn: 298718
This commit is contained in:
Valery Pykhtin 2017-03-24 17:49:05 +00:00
parent 5d57752c81
commit e2419dc907
1 changed files with 8 additions and 25 deletions
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33
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
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@ -974,12 +974,7 @@ void SIScheduleBlockCreator::colorMergeIfPossibleSmallGroupsToNextGroup() {
for (unsigned SUNum : DAG->BottomUpIndex2SU) {
SUnit *SU = &DAG->SUnits[SUNum];
unsigned color = CurrentColoring[SU->NodeNum];
std::map<unsigned, unsigned>::iterator Pos = ColorCount.find(color);
if (Pos != ColorCount.end()) {
++ColorCount[color];
} else {
ColorCount[color] = 1;
}
++ColorCount[color];
}
for (unsigned SUNum : DAG->BottomUpIndex2SU) {
@ -1331,13 +1326,7 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
continue;
int PredID = BlocksStruct.TopDownIndex2Block[topoInd];
std::map<unsigned, unsigned>::iterator RegPos =
LiveOutRegsNumUsages[PredID].find(Reg);
if (RegPos != LiveOutRegsNumUsages[PredID].end()) {
++LiveOutRegsNumUsages[PredID][Reg];
} else {
LiveOutRegsNumUsages[PredID][Reg] = 1;
}
++LiveOutRegsNumUsages[PredID][Reg];
}
}
@ -1377,12 +1366,8 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
}
}
if (!Found) {
if (LiveRegsConsumers.find(Reg) == LiveRegsConsumers.end())
LiveRegsConsumers[Reg] = 1;
else
++LiveRegsConsumers[Reg];
}
if (!Found)
++LiveRegsConsumers[Reg];
}
}
@ -1579,12 +1564,10 @@ void SIScheduleBlockScheduler::blockScheduled(SIScheduleBlock *Block) {
LiveOutRegsNumUsages[Block->getID()].begin(),
E = LiveOutRegsNumUsages[Block->getID()].end(); RegI != E; ++RegI) {
std::pair<unsigned, unsigned> RegP = *RegI;
if (LiveRegsConsumers.find(RegP.first) == LiveRegsConsumers.end())
LiveRegsConsumers[RegP.first] = RegP.second;
else {
assert(LiveRegsConsumers[RegP.first] == 0);
LiveRegsConsumers[RegP.first] += RegP.second;
}
// We produce this register, thus it must not be previously alive.
assert(LiveRegsConsumers.find(RegP.first) == LiveRegsConsumers.end() ||
LiveRegsConsumers[RegP.first] == 0);
LiveRegsConsumers[RegP.first] += RegP.second;
}
if (LastPosHighLatencyParentScheduled[Block->getID()] >
(unsigned)LastPosWaitedHighLatency)