forked from OSchip/llvm-project
[InstCombine] Add test cases for D51236. NFC
llvm-svn: 340789
This commit is contained in:
Craig Topper
parent
35c4702773
commit
e23e8a4f53
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@ -68,4 +68,134 @@ define i64 @test4(i32 %V) {
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ret i64 %zext
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}
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define i64 @test5(i32 %V) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw i32 [[ASHR]], 1073741823
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; CHECK-NEXT: [[ADD:%.*]] = sext i32 [[ADDCONV]] to i64
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%ashr = ashr i32 %V, 1
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%sext = sext i32 %ashr to i64
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%add = add i64 %sext, 1073741823
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ret i64 %add
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}
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define <2 x i64> @test5_splat(<2 x i32> %V) {
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; CHECK-LABEL: @test5_splat(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 1073741823, i64 1073741823>
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%add = add <2 x i64> %sext, <i64 1073741823, i64 1073741823>
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ret <2 x i64> %add
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}
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define <2 x i64> @test5_vec(<2 x i32> %V) {
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; CHECK-LABEL: @test5_vec(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 1, i64 2>
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%add = add <2 x i64> %sext, <i64 1, i64 2>
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ret <2 x i64> %add
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}
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define i64 @test6(i32 %V) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[ADDCONV:%.*]] = add nsw i32 [[ASHR]], -1073741824
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; CHECK-NEXT: [[ADD:%.*]] = sext i32 [[ADDCONV]] to i64
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%ashr = ashr i32 %V, 1
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%sext = sext i32 %ashr to i64
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%add = add i64 %sext, -1073741824
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ret i64 %add
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}
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define <2 x i64> @test6_splat(<2 x i32> %V) {
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; CHECK-LABEL: @test6_splat(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 -1073741824, i64 -1073741824>
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%add = add <2 x i64> %sext, <i64 -1073741824, i64 -1073741824>
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ret <2 x i64> %add
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}
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define <2 x i64> @test6_vec(<2 x i32> %V) {
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; CHECK-LABEL: @test6_vec(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 -1, i64 -2>
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%add = add <2 x i64> %sext, <i64 -1, i64 -2>
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ret <2 x i64> %add
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}
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define <2 x i64> @test6_vec2(<2 x i32> %V) {
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; CHECK-LABEL: @test6_vec2(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i64> [[SEXT]], <i64 -1, i64 1>
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%ashr = ashr <2 x i32> %V, <i32 1, i32 1>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%add = add <2 x i64> %sext, <i64 -1, i64 1>
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ret <2 x i64> %add
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}
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define i64 @test7(i32 %V) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[V:%.*]], 1
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; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw i32 [[LSHR]], 2147483647
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; CHECK-NEXT: [[ADD:%.*]] = zext i32 [[ADDCONV]] to i64
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; CHECK-NEXT: ret i64 [[ADD]]
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;
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%lshr = lshr i32 %V, 1
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%zext = zext i32 %lshr to i64
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%add = add i64 %zext, 2147483647
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ret i64 %add
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}
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define <2 x i64> @test7_splat(<2 x i32> %V) {
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; CHECK-LABEL: @test7_splat(
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; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], <i64 2147483647, i64 2147483647>
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%lshr = lshr <2 x i32> %V, <i32 1, i32 1>
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%zext = zext <2 x i32> %lshr to <2 x i64>
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%add = add <2 x i64> %zext, <i64 2147483647, i64 2147483647>
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ret <2 x i64> %add
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}
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define <2 x i64> @test7_vec(<2 x i32> %V) {
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; CHECK-LABEL: @test7_vec(
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; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], <i64 1, i64 2>
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; CHECK-NEXT: ret <2 x i64> [[ADD]]
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;
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%lshr = lshr <2 x i32> %V, <i32 1, i32 1>
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%zext = zext <2 x i32> %lshr to <2 x i64>
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%add = add <2 x i64> %zext, <i64 1, i64 2>
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ret <2 x i64> %add
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}
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!0 = !{ i32 0, i32 2000 }
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