forked from OSchip/llvm-project
The divide unit is not pipeline, but it is still buffered.
Buffered means a later divide may be executed out-of-order while a prior divide is sitting (buffered) in a reservation station. You can tell it's not pipelined, because operations that use it reserve it for more than one cycle: def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { let Latency = 25; let ResourceCycles = [1, 10]; } We don't currently distinguish between an unpipeline operation and one that is split into multiple micro-ops requiring the same unit. Except that the later may have NumMicroOps > 1 if they also consume issue/dispatch resources. llvm-svn: 178519
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@ -50,8 +50,8 @@ def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
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def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
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def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
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// Integer division issued on port 0, but uses the non-pipelined divider.
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def HWDivider : ProcResource<1> { let Buffered = 0; }
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// Integer division issued on port 0.
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def HWDivider : ProcResource<1>;
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// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
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// cycles after the memory operand.
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@ -46,8 +46,8 @@ def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
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def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
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def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
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// Integer division issued on port 0, but uses the non-pipelined divider.
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def SBDivider : ProcResource<1> { let Buffered = 0; }
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// Integer division issued on port 0.
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def SBDivider : ProcResource<1>;
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// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
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// cycles after the memory operand.
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