forked from OSchip/llvm-project
[SystemZ] Support vector registers with inline asm
Allow using vector register names and the "v" constraint in inline asm to ensure compatibility with GCC. llvm-svn: 322562
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@ -30,15 +30,30 @@ const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
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};
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const char *const SystemZTargetInfo::GCCRegNames[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
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"r11", "r12", "r13", "r14", "r15", "f0", "f2", "f4", "f6", "f1", "f3",
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"f5", "f7", "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
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"f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15",
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/*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1",
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"v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
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"v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
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};
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const TargetInfo::AddlRegName GCCAddlRegNames[] = {
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{{"v0"}, 16}, {{"v2"}, 17}, {{"v4"}, 18}, {{"v6"}, 19},
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{{"v1"}, 20}, {{"v3"}, 21}, {{"v5"}, 22}, {{"v7"}, 23},
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{{"v8"}, 24}, {{"v10"}, 25}, {{"v12"}, 26}, {{"v14"}, 27},
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{{"v9"}, 28}, {{"v11"}, 29}, {{"v13"}, 30}, {{"v15"}, 31}
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};
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ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
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return llvm::makeArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
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return llvm::makeArrayRef(GCCAddlRegNames);
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}
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bool SystemZTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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switch (*Name) {
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@ -48,6 +63,7 @@ bool SystemZTargetInfo::validateAsmConstraint(
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case 'a': // Address register
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case 'd': // Data register (equivalent to 'r')
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case 'f': // Floating-point register
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case 'v': // Vector register
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Info.setAllowsRegister();
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return true;
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@ -62,6 +62,8 @@ public:
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return None;
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}
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ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &info) const override;
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