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[ARM][Thumb2] Refresh UXTB16 tests to match optimized IR from instcombine 

As discussed on D77804, instcombine will have already performed a similar SimplifyMultipleUseDemandedBits call which will break the UXTB16 pattern that was being match in these DAG tests

I've updated the existing tests so that it match the instcombine IR (with a suitable FIXME) and added an equivalent test pattern suggested by @dmgreen
This commit is contained in:
Simon Pilgrim 2022-06-01 15:25:58 +01:00
parent 3a07280290
commit e1d02f6c37
2 changed files with 61 additions and 17 deletions
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28
llvm/test/CodeGen/ARM/uxtb.ll
View File

@ -99,21 +99,39 @@ define i32 @test9(i32 %x) {
ret i32 %tmp6
}
; FIXME: Failed to match uxtb16
define i32 @test10(i32 %p0) {
; CHECK-LABEL: test10:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r1, #248
; CHECK-NEXT: mov r2, #7
; CHECK-NEXT: orr r1, r1, #16252928
; CHECK-NEXT: and r0, r1, r0, lsr #7
; CHECK-NEXT: lsr r1, r0, #5
; CHECK-NEXT: uxtb16 r1, r1
; CHECK-NEXT: orr r0, r1, r0
; CHECK-NEXT: orr r2, r2, #458752
; CHECK-NEXT: and r1, r1, r0, lsr #7
; CHECK-NEXT: and r0, r2, r0, lsr #12
; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: bx lr
%tmp1 = lshr i32 %p0, 7
%tmp2 = and i32 %tmp1, 16253176
%tmp4 = lshr i32 %tmp2, 5
%tmp4 = lshr i32 %p0, 12
%tmp5 = and i32 %tmp4, 458759
%tmp7 = or i32 %tmp5, %tmp2
ret i32 %tmp7
}
define i32 @test11(i32 %p0) {
; CHECK-LABEL: test11:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r1, #1
; CHECK-NEXT: and r0, r0, #3
; CHECK-NEXT: orr r1, r1, #65536
; CHECK-NEXT: lsl r0, r1, r0
; CHECK-NEXT: lsr r0, r0, #1
; CHECK-NEXT: uxtb16 r0, r0
; CHECK-NEXT: bx lr
%p = and i32 %p0, 3
%a = shl i32 65537, %p
%b = lshr i32 %a, 1
%tmp7 = and i32 %b, 458759
ret i32 %tmp7
}

50
llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
View File

@ -158,29 +158,55 @@ define i32 @test9(i32 %x) {
ret i32 %tmp6
}
; FIXME: Failed to match uxtb16
define i32 @test10(i32 %p0) {
; CHECK-DSP-LABEL: test10:
; CHECK-DSP: @ %bb.0:
; CHECK-DSP-NEXT: mov.w r1, #16253176
; CHECK-DSP-NEXT: and.w r0, r1, r0, lsr #7
; CHECK-DSP-NEXT: lsrs r1, r0, #5
; CHECK-DSP-NEXT: uxtb16 r1, r1
; CHECK-DSP-NEXT: mov.w r2, #458759
; CHECK-DSP-NEXT: and.w r1, r1, r0, lsr #7
; CHECK-DSP-NEXT: and.w r0, r2, r0, lsr #12
; CHECK-DSP-NEXT: add r0, r1
; CHECK-DSP-NEXT: bx lr
;
; CHECK-NO-DSP-LABEL: test10:
; CHECK-NO-DSP: @ %bb.0:
; CHECK-NO-DSP-NEXT: mov.w r1, #16253176
; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, lsr #7
; CHECK-NO-DSP-NEXT: mov.w r1, #458759
; CHECK-NO-DSP-NEXT: and.w r1, r1, r0, lsr #5
; CHECK-NO-DSP-NEXT: mov.w r2, #458759
; CHECK-NO-DSP-NEXT: and.w r1, r1, r0, lsr #7
; CHECK-NO-DSP-NEXT: and.w r0, r2, r0, lsr #12
; CHECK-NO-DSP-NEXT: add r0, r1
; CHECK-NO-DSP-NEXT: bx lr
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
%tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1]
%tmp5 = and i32 %tmp4, 458759 ; <i32> [#uses=1]
%tmp7 = or i32 %tmp5, %tmp2 ; <i32> [#uses=1]
%tmp1 = lshr i32 %p0, 7
%tmp2 = and i32 %tmp1, 16253176
%tmp4 = lshr i32 %p0, 12
%tmp5 = and i32 %tmp4, 458759
%tmp7 = or i32 %tmp5, %tmp2
ret i32 %tmp7
}
define i32 @test11(i32 %p0) {
; CHECK-DSP-LABEL: test11:
; CHECK-DSP: @ %bb.0:
; CHECK-DSP-NEXT: and r0, r0, #3
; CHECK-DSP-NEXT: mov.w r1, #65537
; CHECK-DSP-NEXT: lsl.w r0, r1, r0
; CHECK-DSP-NEXT: lsrs r0, r0, #1
; CHECK-DSP-NEXT: uxtb16 r0, r0
; CHECK-DSP-NEXT: bx lr
;
; CHECK-NO-DSP-LABEL: test11:
; CHECK-NO-DSP: @ %bb.0:
; CHECK-NO-DSP-NEXT: and r0, r0, #3
; CHECK-NO-DSP-NEXT: mov.w r1, #65537
; CHECK-NO-DSP-NEXT: lsl.w r0, r1, r0
; CHECK-NO-DSP-NEXT: mov.w r1, #458759
; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, lsr #1
; CHECK-NO-DSP-NEXT: bx lr
%p = and i32 %p0, 3
%a = shl i32 65537, %p
%b = lshr i32 %a, 1
%tmp7 = and i32 %b, 458759
ret i32 %tmp7
}