forked from OSchip/llvm-project
Misc. APInt-ification in the DAGCombiner.
llvm-svn: 47869
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10f34077f1
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e1c4f99549
llvm/lib/CodeGen/SelectionDAG
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@ -1984,15 +1984,15 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
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// If there is an AND of either shifted operand, apply it to the result.
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if (LHSMask.Val || RHSMask.Val) {
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uint64_t Mask = MVT::getIntVTBitMask(VT);
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APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
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if (LHSMask.Val) {
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uint64_t RHSBits = (1ULL << LShVal)-1;
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Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
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APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
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Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
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}
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if (RHSMask.Val) {
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uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
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Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
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APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
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Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
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}
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Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
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@ -2248,8 +2248,8 @@ SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
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// the constant which would cause it to be modified for this
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// operation.
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if (N->getOpcode() == ISD::SRA) {
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uint64_t BinOpRHSSign = BinOpCst->getValue() >> (MVT::getSizeInBits(VT)-1);
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if ((bool)BinOpRHSSign != HighBitSet)
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bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
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if (BinOpRHSSignSet != HighBitSet)
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return SDOperand();
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}
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@ -2872,7 +2872,8 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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} else if (X.getValueType() > VT) {
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X = DAG.getNode(ISD::TRUNCATE, VT, X);
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}
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uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
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APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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Mask.zext(MVT::getSizeInBits(VT));
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return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
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}
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@ -2988,7 +2989,8 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
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} else if (X.getValueType() > VT) {
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X = DAG.getNode(ISD::TRUNCATE, VT, X);
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}
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uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
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APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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Mask.zext(MVT::getSizeInBits(VT));
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return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
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}
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@ -3350,7 +3352,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
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SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
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AddToWorkList(NewConv.Val);
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT));
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if (N0.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
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assert(N0.getOpcode() == ISD::FABS);
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@ -3383,7 +3385,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
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AddToWorkList(X.Val);
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}
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uint64_t SignBit = MVT::getIntVTSignBit(VT);
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APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT));
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X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
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AddToWorkList(X.Val);
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@ -3457,7 +3459,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
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for (unsigned i = 0, e = BV->getNumOperands(); i != e;
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i += NumInputsPerOutput) {
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bool isLE = TLI.isLittleEndian();
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uint64_t NewBits = 0;
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APInt NewBits = APInt(DstBitSize, 0);
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bool EltIsUndef = true;
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for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
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// Shift the previously computed bits over.
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@ -3466,7 +3468,8 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
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if (Op.getOpcode() == ISD::UNDEF) continue;
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EltIsUndef = false;
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NewBits |= cast<ConstantSDNode>(Op)->getValue();
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NewBits |=
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APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize);
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}
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if (EltIsUndef)
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@ -3492,14 +3495,14 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
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Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
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continue;
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}
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uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
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APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue();
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for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
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unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
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APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
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Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
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if (isS2V && i == 0 && j == 0 && ThisVal == OpVal)
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if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
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// Simply turn this into a SCALAR_TO_VECTOR of the new type.
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return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]);
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OpVal >>= DstBitSize;
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OpVal = OpVal.lshr(DstBitSize);
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}
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// For big endian targets, swap the order of the pieces of each element.
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