forked from OSchip/llvm-project
[HIP] Support -fcuda-flush-denormals-to-zero for amdgcn
Differential Revision: https://reviews.llvm.org/D48287 llvm-svn: 337639
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@ -209,7 +209,6 @@ LANGOPT(RenderScript , 1, 0, "RenderScript")
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LANGOPT(CUDAIsDevice , 1, 0, "compiling for CUDA device")
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LANGOPT(CUDAAllowVariadicFunctions, 1, 0, "allowing variadic functions in CUDA device code")
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LANGOPT(CUDAHostDeviceConstexpr, 1, 1, "treating unattributed constexpr functions as __host__ __device__")
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LANGOPT(CUDADeviceFlushDenormalsToZero, 1, 0, "flushing denormals to zero")
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LANGOPT(CUDADeviceApproxTranscendentals, 1, 0, "using approximate transcendental functions")
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LANGOPT(CUDARelocatableDeviceCode, 1, 0, "generate relocatable device code")
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@ -1800,7 +1800,7 @@ void CodeGenModule::ConstructDefaultFnAttrList(StringRef Name, bool HasOptnone,
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FuncAttrs.addAttribute(llvm::Attribute::NoUnwind);
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// Respect -fcuda-flush-denormals-to-zero.
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if (getLangOpts().CUDADeviceFlushDenormalsToZero)
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if (CodeGenOpts.FlushDenorm)
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FuncAttrs.addAttribute("nvptx-f32ftz", "true");
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}
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}
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@ -526,7 +526,7 @@ void CodeGenModule::Release() {
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// floating point values to 0. (This corresponds to its "__CUDA_FTZ"
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// property.)
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getModule().addModuleFlag(llvm::Module::Override, "nvvm-reflect-ftz",
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LangOpts.CUDADeviceFlushDenormalsToZero ? 1 : 0);
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CodeGenOpts.FlushDenorm ? 1 : 0);
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}
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// Emit OpenCL specific module metadata: OpenCL/SPIR version.
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@ -690,7 +690,9 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
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Args.hasArg(OPT_cl_unsafe_math_optimizations) ||
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Args.hasArg(OPT_cl_fast_relaxed_math));
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Opts.Reassociate = Args.hasArg(OPT_mreassociate);
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Opts.FlushDenorm = Args.hasArg(OPT_cl_denorms_are_zero);
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Opts.FlushDenorm = Args.hasArg(OPT_cl_denorms_are_zero) ||
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(Args.hasArg(OPT_fcuda_is_device) &&
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Args.hasArg(OPT_fcuda_flush_denormals_to_zero));
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Opts.CorrectlyRoundedDivSqrt =
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Args.hasArg(OPT_cl_fp32_correctly_rounded_divide_sqrt);
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Opts.UniformWGSize =
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@ -2191,9 +2193,6 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
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if (Args.hasArg(OPT_fno_cuda_host_device_constexpr))
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Opts.CUDAHostDeviceConstexpr = 0;
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if (Opts.CUDAIsDevice && Args.hasArg(OPT_fcuda_flush_denormals_to_zero))
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Opts.CUDADeviceFlushDenormalsToZero = 1;
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if (Opts.CUDAIsDevice && Args.hasArg(OPT_fcuda_approx_transcendentals))
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Opts.CUDADeviceApproxTranscendentals = 1;
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@ -5,6 +5,13 @@
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// RUN: -triple nvptx-nvidia-cuda -emit-llvm -o - %s | \
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// RUN: FileCheck %s -check-prefix CHECK -check-prefix FTZ
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// RUN: %clang_cc1 -fcuda-is-device -x hip \
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// RUN: -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm -o - %s | \
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// RUN: FileCheck %s -check-prefix CHECK -check-prefix AMDNOFTZ
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// RUN: %clang_cc1 -fcuda-is-device -x hip -fcuda-flush-denormals-to-zero \
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// RUN: -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm -o - %s | \
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// RUN: FileCheck %s -check-prefix CHECK -check-prefix AMDFTZ
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#include "Inputs/cuda.h"
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// Checks that device function calls get emitted with the "ntpvx-f32ftz"
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@ -12,11 +19,19 @@
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// -fcuda-flush-denormals-to-zero. Further, check that we reflect the presence
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// or absence of -fcuda-flush-denormals-to-zero in a module flag.
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// AMDGCN targets always have +fp64-fp16-denormals.
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// AMDGCN targets without fast FMAF (e.g. gfx803) always have +fp32-denormals.
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// For AMDGCN target with fast FMAF (e.g. gfx900), it has +fp32-denormals
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// by default and -fp32-denormals when there is option
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// -fcuda-flush-denormals-to-zero.
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// CHECK-LABEL: define void @foo() #0
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extern "C" __device__ void foo() {}
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// FTZ: attributes #0 = {{.*}} "nvptx-f32ftz"="true"
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// NOFTZ-NOT: attributes #0 = {{.*}} "nvptx-f32ftz"
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// AMDNOFTZ: attributes #0 = {{.*}}+fp32-denormals{{.*}}+fp64-fp16-denormals
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// AMDFTZ: attributes #0 = {{.*}}+fp64-fp16-denormals{{.*}}-fp32-denormals
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// FTZ:!llvm.module.flags = !{{{.*}}[[MODFLAG:![0-9]+]]}
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// FTZ:[[MODFLAG]] = !{i32 4, !"nvvm-reflect-ftz", i32 1}
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