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[X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a couple scheduler models. 

llvm-svn: 327821
This commit is contained in:
Craig Topper 2018-03-19 04:21:42 +00:00
parent d10ceffa5f
commit e18fbab988
2 changed files with 2 additions and 4 deletions
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3
llvm/lib/Target/X86/X86SchedSandyBridge.td
View File

@ -1055,8 +1055,7 @@ def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>;
def: InstRW<[SBWriteResGroup25], (instregex "OUT32rr")>;
def: InstRW<[SBWriteResGroup25], (instregex "OUT8rr")>;
def: InstRW<[SBWriteResGroup25], (instregex "XADD(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup25], (instregex "XADD8rr")>;
def: InstRW<[SBWriteResGroup25], (instregex "XADD(8|16|32|64)rr")>;
def SBWriteResGroup25_2 : SchedWriteRes<[SBPort5,SBPort05]> {
let Latency = 3;

3
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -2105,8 +2105,7 @@ def SKXWriteResGroup36 : SchedWriteRes<[SKXPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SKXWriteResGroup36], (instregex "XADD(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup36], (instregex "XADD8rr")>;
def: InstRW<[SKXWriteResGroup36], (instregex "XADD(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup36], (instregex "XCHG8rr")>;
def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {