forked from OSchip/llvm-project
[mips] Enable IAS by default for 32-bit MIPS targets (O32).
Summary: The MIPS IAS can now pass 'ninja check-all', recurse, build a bootable linux kernel, and pass a variety of LNT testing. Unfortunately we can't enable it by default for 64-bit targets yet since the N32 ABI is still very buggy and this also means we can't enable it for N64 either because we can't distinguish between N32 and N64 in the relevant code. Reviewers: vkalintiris Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D18759 Differential Revision: http://reviews.llvm.org/D18761 llvm-svn: 269560
This commit is contained in:
Daniel Sanders
parent
81b08dedde
commit
e160f83f71
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@ -2444,6 +2444,8 @@ bool Generic_GCC::IsIntegratedAssemblerDefault() const {
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case llvm::Triple::ppc64:
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case llvm::Triple::ppc64le:
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case llvm::Triple::systemz:
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case llvm::Triple::mips:
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case llvm::Triple::mipsel:
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return true;
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default:
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return false;
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@ -42,4 +42,9 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
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SupportsDebugInformation = true;
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ExceptionsType = ExceptionHandling::DwarfCFI;
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DwarfRegNumForCFI = true;
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// Enable IAS by default for O32.
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if (TheTriple.getArch() == Triple::mips ||
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TheTriple.getArch() == Triple::mipsel)
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UseIntegratedAssembler = true;
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}
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@ -820,7 +820,7 @@ declare void @v_df_df(double, double) #1
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declare float @sf_v() #1
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; stel: .section .mips16.call.fp.sf_v,"ax",@progbits
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; stel: .ent __call_stub_fp_sf_v
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; stel: move $18, $31
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; stel: move $18, $ra
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; stel: jal sf_v
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; stel: mfc1 $2, $f0
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; stel: jr $18
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@ -898,7 +898,7 @@ declare float @sf_df_df(double, double) #1
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declare double @df_v() #1
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; stel: .section .mips16.call.fp.df_v,"ax",@progbits
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; stel: .ent __call_stub_fp_df_v
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; stel: move $18, $31
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; stel: move $18, $ra
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; stel: jal df_v
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; stel: mfc1 $2, $f0
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; stel: mfc1 $3, $f1
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@ -983,7 +983,7 @@ declare double @df_df_df(double, double) #1
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declare { float, float } @sc_v() #1
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; stel: .section .mips16.call.fp.sc_v,"ax",@progbits
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; stel: .ent __call_stub_fp_sc_v
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; stel: move $18, $31
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; stel: move $18, $ra
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; stel: jal sc_v
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; stel: mfc1 $2, $f0
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; stel: mfc1 $3, $f2
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@ -1004,7 +1004,7 @@ declare { float, float } @sc_sf(float) #1
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declare { double, double } @dc_v() #1
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; stel: .section .mips16.call.fp.dc_v,"ax",@progbits
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; stel: .ent __call_stub_fp_dc_v
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; stel: move $18, $31
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; stel: move $18, $ra
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; stel: jal dc_v
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; stel: mfc1 $4, $f2
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; stel: mfc1 $5, $f3
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@ -20,7 +20,8 @@ entry:
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}
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; stel: .section .mips16.fn.v_sf,"ax",@progbits
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; stel: .ent __fn_stub_v_sf
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; stel: la $25, v_sf
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; stel: lui $25, %hi(v_sf)
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; stel: addiu $25, $25, %lo(v_sf)
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; stel: mfc1 $4, $f12
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; stel: jr $25
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; stel: __fn_local_v_sf = v_sf
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@ -40,7 +41,8 @@ entry:
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; stel: .section .mips16.fn.v_df,"ax",@progbits
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; stel: .ent __fn_stub_v_df
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; stel: la $25, v_df
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; stel: lui $25, %hi(v_df)
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; stel: addiu $25, $25, %lo(v_df)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f13
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; stel: jr $25
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@ -63,7 +65,8 @@ entry:
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; stel: .section .mips16.fn.v_sf_sf,"ax",@progbits
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; stel: .ent __fn_stub_v_sf_sf
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; stel: la $25, v_sf_sf
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; stel: lui $25, %hi(v_sf_sf)
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; stel: addiu $25, $25, %lo(v_sf_sf)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f14
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; stel: jr $25
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@ -86,7 +89,8 @@ entry:
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; stel: .section .mips16.fn.v_sf_df,"ax",@progbits
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; stel: .ent __fn_stub_v_sf_df
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; stel: la $25, v_sf_df
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; stel: lui $25, %hi(v_sf_df)
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; stel: addiu $25, $25, %lo(v_sf_df)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $6, $f14
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; stel: mfc1 $7, $f15
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@ -110,7 +114,8 @@ entry:
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; stel: .section .mips16.fn.v_df_sf,"ax",@progbits
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; stel: .ent __fn_stub_v_df_sf
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; stel: la $25, v_df_sf
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; stel: lui $25, %hi(v_df_sf)
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; stel: addiu $25, $25, %lo(v_df_sf)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f13
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; stel: mfc1 $6, $f14
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@ -134,7 +139,8 @@ entry:
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; stel: .section .mips16.fn.v_df_df,"ax",@progbits
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; stel: .ent __fn_stub_v_df_df
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; stel: la $25, v_df_df
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; stel: lui $25, %hi(v_df_df)
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; stel: addiu $25, $25, %lo(v_df_df)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f13
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; stel: mfc1 $6, $f14
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@ -164,7 +170,8 @@ entry:
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; stel: .section .mips16.fn.sf_sf,"ax",@progbits
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; stel: .ent __fn_stub_sf_sf
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; stel: la $25, sf_sf
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; stel: lui $25, %hi(sf_sf)
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; stel: addiu $25, $25, %lo(sf_sf)
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; stel: mfc1 $4, $f12
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; stel: jr $25
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; stel: __fn_local_sf_sf = sf_sf
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@ -184,7 +191,8 @@ entry:
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; stel: .section .mips16.fn.sf_df,"ax",@progbits
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; stel: .ent __fn_stub_sf_df
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; stel: la $25, sf_df
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; stel: lui $25, %hi(sf_df)
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; stel: addiu $25, $25, %lo(sf_df)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f13
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; stel: jr $25
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@ -208,7 +216,8 @@ entry:
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; stel: .section .mips16.fn.sf_sf_sf,"ax",@progbits
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; stel: .ent __fn_stub_sf_sf_sf
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; stel: la $25, sf_sf_sf
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; stel: lui $25, %hi(sf_sf_sf)
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; stel: addiu $25, $25, %lo(sf_sf_sf)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f14
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; stel: jr $25
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@ -232,7 +241,8 @@ entry:
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; stel: .section .mips16.fn.sf_sf_df,"ax",@progbits
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; stel: .ent __fn_stub_sf_sf_df
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; stel: la $25, sf_sf_df
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; stel: lui $25, %hi(sf_sf_df)
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; stel: addiu $25, $25, %lo(sf_sf_df)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $6, $f14
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; stel: mfc1 $7, $f15
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@ -257,7 +267,8 @@ entry:
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; stel: .section .mips16.fn.sf_df_sf,"ax",@progbits
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; stel: .ent __fn_stub_sf_df_sf
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; stel: la $25, sf_df_sf
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; stel: lui $25, %hi(sf_df_sf)
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; stel: addiu $25, $25, %lo(sf_df_sf)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f13
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; stel: mfc1 $6, $f14
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@ -282,7 +293,8 @@ entry:
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; stel: .section .mips16.fn.sf_df_df,"ax",@progbits
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; stel: .ent __fn_stub_sf_df_df
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; stel: la $25, sf_df_df
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; stel: lui $25, %hi(sf_df_df)
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; stel: addiu $25, $25, %lo(sf_df_df)
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; stel: mfc1 $4, $f12
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; stel: mfc1 $5, $f13
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; stel: mfc1 $6, $f14
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@ -1,4 +1,11 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picfp16
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \
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; RUN: -relocation-model=pic -no-integrated-as < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=GAS
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; The integrated assembler expands assembly macros before printing.
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \
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; RUN: -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=IAS
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@x = external global float
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@ -11,11 +18,13 @@ entry:
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store float %0, float* @x, align 4
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ret void
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}
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; picfp16: .ent __fn_stub_v_sf
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; picfp16: .cpload $25
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; picfp16: .set reorder
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; picfp16: .reloc 0, R_MIPS_NONE, v_sf
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; picfp16: la $25, $__fn_local_v_sf
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; picfp16: mfc1 $4, $f12
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; picfp16: jr $25
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; picfp16: .end __fn_stub_v_sf
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; ALL-LABEL: .ent __fn_stub_v_sf
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; ALL: .cpload $25
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; ALL: .set reorder
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; ALL: .reloc 0, R_MIPS_NONE, v_sf
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; GAS: la $25, $__fn_local_v_sf
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; IAS: lui $25, %hi($$__fn_local_v_sf)
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; IAS: addiu $25, $25, %lo($$__fn_local_v_sf)
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; ALL: mfc1 $4, $f12
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; ALL: jr $25
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; ALL: .end __fn_stub_v_sf
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@ -5,6 +5,12 @@
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; RUN: llc -no-integrated-as -march=mips -relocation-model=pic < %s | \
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; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s
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; IAS might not print in the same way since it parses the assembly.
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; RUN: llc -march=mipsel -relocation-model=pic < %s | \
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; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=IAS %s
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; RUN: llc -march=mips -relocation-model=pic < %s | \
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; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=IAS %s
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%union.u_tag = type { i64 }
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%struct.anon = type { i32, i32 }
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@uval = common global %union.u_tag zeroinitializer, align 8
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@ -15,6 +21,7 @@ entry:
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; ALL-LABEL: constraint_X:
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; ALL: #APP
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; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
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; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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@ -26,6 +33,9 @@ entry:
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; ALL-LABEL: constraint_x:
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; ALL: #APP
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; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
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; This is _also_ -3 because uimm16 values are silently coerced to simm16 when
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; it would otherwise fail to match.
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; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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@ -54,39 +64,66 @@ entry:
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}
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; z with -3
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define i32 @constraint_z() nounwind {
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define void @constraint_z_0() nounwind {
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entry:
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; ALL-LABEL: constraint_z:
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; ALL-LABEL: constraint_z_0:
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; ALL: #APP
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; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
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ret void
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}
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; z with 0
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define void @constraint_z_1() nounwind {
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entry:
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; ALL-LABEL: constraint_z_1:
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; ALL: #APP
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; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
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; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, $0
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; IAS: move ${{[0-9]+}}, ${{[0-9]+}}
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
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tail call i32 asm sideeffect "addu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
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ret void
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}
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; z with non-zero and the "r"(register) and "J"(integer zero) constraints
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define void @constraint_z_2() nounwind {
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entry:
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; ALL-LABEL: constraint_z_2:
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; ALL: #APP
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; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
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ret void
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}
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; z with zero and the "r"(register) and "J"(integer zero) constraints
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define void @constraint_z_3() nounwind {
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entry:
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; ALL-LABEL: constraint_z_3:
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; ALL: #APP
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; ALL: mtc0 $0, ${{[0-9]+}}
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; GAS: mtc0 $0, ${{[0-9]+}}
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; IAS: mtc0 $zero, ${{[0-9]+}}, 0
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
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ret void
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}
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; z with non-zero and just the "r"(register) constraint
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define void @constraint_z_4() nounwind {
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entry:
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; ALL-LABEL: constraint_z_4:
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; ALL: #APP
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; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
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ret void
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}
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; z with zero and just the "r"(register) constraint
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define void @constraint_z_5() nounwind {
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entry:
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; ALL-LABEL: constraint_z_5:
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; FIXME: Check for $0, instead of other registers.
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; We should be using $0 directly in this case, not real registers.
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; When the materialization of 0 gets fixed, this test will fail.
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@ -94,7 +131,7 @@ entry:
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; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
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ret i32 0
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ret void
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}
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; A long long in 32 bit mode (use to assert)
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@ -1,5 +1,6 @@
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; RUN: llc -no-integrated-as -march=mipsel < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=GAS
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=ALL -check-prefix=IAS
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define void @constraint_I() nounwind {
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; First I with short
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@ -31,6 +32,7 @@ define void @constraint_K() nounwind {
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; Now K with 64
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; ALL: #APP
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; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64
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; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 64
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; ALL: #NO_APP
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tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
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ret void
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