forked from OSchip/llvm-project
AMDGPU: Annotate features from x work item/group IDs.
This wasn't necessary before since they are always enabled for kernels, but this is necessary if they need to be forwarded to a callable function. llvm-svn: 308226
This commit is contained in:
Matt Arsenault
parent
e59dd00038
commit
e15855d9e3
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@ -129,8 +129,16 @@ bool AMDGPUAnnotateKernelFeatures::visitConstantExprsRecursively(
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//
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// TODO: We should not add the attributes if the known compile time workgroup
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// size is 1 for y/z.
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static StringRef intrinsicToAttrName(Intrinsic::ID ID, bool &IsQueuePtr) {
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static StringRef intrinsicToAttrName(Intrinsic::ID ID,
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bool &NonKernelOnly,
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bool &IsQueuePtr) {
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switch (ID) {
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case Intrinsic::amdgcn_workitem_id_x:
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NonKernelOnly = true;
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return "amdgpu-work-item-id-x";
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case Intrinsic::amdgcn_workgroup_id_x:
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NonKernelOnly = true;
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return "amdgpu-work-group-id-x";
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case Intrinsic::amdgcn_workitem_id_y:
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case Intrinsic::r600_read_tidig_y:
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return "amdgpu-work-item-id-y";
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@ -172,12 +180,12 @@ static bool handleAttr(Function &Parent, const Function &Callee,
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static void copyFeaturesToFunction(Function &Parent, const Function &Callee,
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bool &NeedQueuePtr) {
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// X ids unnecessarily propagated to kernels.
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static const StringRef AttrNames[] = {
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// .x omitted
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{ "amdgpu-work-item-id-x" },
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{ "amdgpu-work-item-id-y" },
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{ "amdgpu-work-item-id-z" },
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// .x omitted
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{ "amdgpu-work-group-id-x" },
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{ "amdgpu-work-group-id-y" },
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{ "amdgpu-work-group-id-z" },
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{ "amdgpu-dispatch-ptr" },
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@ -198,6 +206,7 @@ bool AMDGPUAnnotateKernelFeatures::addFeatureAttributes(Function &F) {
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bool Changed = false;
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bool NeedQueuePtr = false;
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bool IsFunc = !AMDGPU::isEntryFunctionCC(F.getCallingConv());
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for (BasicBlock &BB : F) {
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for (Instruction &I : BB) {
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@ -214,8 +223,10 @@ bool AMDGPUAnnotateKernelFeatures::addFeatureAttributes(Function &F) {
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copyFeaturesToFunction(F, *Callee, NeedQueuePtr);
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Changed = true;
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} else {
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StringRef AttrName = intrinsicToAttrName(IID, NeedQueuePtr);
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if (!AttrName.empty()) {
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bool NonKernelOnly = false;
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StringRef AttrName = intrinsicToAttrName(IID,
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NonKernelOnly, NeedQueuePtr);
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if (!AttrName.empty() && (IsFunc || !NonKernelOnly)) {
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F.addFnAttr(AttrName);
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Changed = true;
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}
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@ -42,6 +42,9 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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WorkGroupIDZSystemSGPR(AMDGPU::NoRegister),
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WorkGroupInfoSystemSGPR(AMDGPU::NoRegister),
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PrivateSegmentWaveByteOffsetSystemSGPR(AMDGPU::NoRegister),
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WorkItemIDXVGPR(AMDGPU::NoRegister),
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WorkItemIDYVGPR(AMDGPU::NoRegister),
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WorkItemIDZVGPR(AMDGPU::NoRegister),
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PSInputAddr(0),
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PSInputEnable(0),
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ReturnsVoid(true),
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@ -87,7 +90,6 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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ScratchWaveOffsetReg = AMDGPU::SGPR4;
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FrameOffsetReg = AMDGPU::SGPR5;
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StackPtrOffsetReg = AMDGPU::SGPR32;
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return;
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}
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CallingConv::ID CC = F->getCallingConv();
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@ -101,17 +103,25 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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if (ST.debuggerEmitPrologue()) {
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// Enable everything.
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WorkGroupIDX = true;
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WorkGroupIDY = true;
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WorkGroupIDZ = true;
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WorkItemIDX = true;
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WorkItemIDY = true;
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WorkItemIDZ = true;
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} else {
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if (F->hasFnAttribute("amdgpu-work-group-id-x"))
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WorkGroupIDX = true;
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if (F->hasFnAttribute("amdgpu-work-group-id-y"))
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WorkGroupIDY = true;
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if (F->hasFnAttribute("amdgpu-work-group-id-z"))
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WorkGroupIDZ = true;
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if (F->hasFnAttribute("amdgpu-work-item-id-x"))
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WorkItemIDX = true;
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if (F->hasFnAttribute("amdgpu-work-item-id-y"))
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WorkItemIDY = true;
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@ -119,22 +129,24 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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WorkItemIDZ = true;
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}
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// X, XY, and XYZ are the only supported combinations, so make sure Y is
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// enabled if Z is.
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if (WorkItemIDZ)
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WorkItemIDY = true;
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const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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bool MaySpill = ST.isVGPRSpillingEnabled(*F);
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bool HasStackObjects = FrameInfo.hasStackObjects() || FrameInfo.hasCalls();
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if (HasStackObjects || MaySpill) {
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PrivateSegmentWaveByteOffset = true;
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if (isEntryFunction()) {
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// X, XY, and XYZ are the only supported combinations, so make sure Y is
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// enabled if Z is.
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if (WorkItemIDZ)
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WorkItemIDY = true;
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// HS and GS always have the scratch wave offset in SGPR5 on GFX9.
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if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
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(CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
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PrivateSegmentWaveByteOffsetSystemSGPR = AMDGPU::SGPR5;
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if (HasStackObjects || MaySpill) {
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PrivateSegmentWaveByteOffset = true;
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// HS and GS always have the scratch wave offset in SGPR5 on GFX9.
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if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
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(CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
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PrivateSegmentWaveByteOffsetSystemSGPR = AMDGPU::SGPR5;
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}
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}
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if (ST.isAmdCodeObjectV2(MF)) {
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@ -160,7 +172,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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// We don't need to worry about accessing spills with flat instructions.
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// TODO: On VI where we must use flat for global, we should be able to omit
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// this if it is never used for generic access.
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if (HasStackObjects && ST.hasFlatAddressSpace() && ST.isAmdHsaOS())
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if (HasStackObjects && ST.hasFlatAddressSpace() && ST.isAmdHsaOS() &&
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isEntryFunction())
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FlatScratchInit = true;
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}
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@ -119,6 +119,11 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
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unsigned WorkGroupInfoSystemSGPR;
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unsigned PrivateSegmentWaveByteOffsetSystemSGPR;
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// VGPR inputs. These are always v0, v1 and v2 for entry functions.
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unsigned WorkItemIDXVGPR;
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unsigned WorkItemIDYVGPR;
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unsigned WorkItemIDZVGPR;
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// Graphics info.
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unsigned PSInputAddr;
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unsigned PSInputEnable;
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@ -1,8 +1,10 @@
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; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.workitem.id.y() #0
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declare i32 @llvm.amdgcn.workitem.id.z() #0
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@ -12,56 +14,70 @@ declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0
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declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0
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declare i64 @llvm.amdgcn.dispatch.id() #0
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; HSA: define void @use_workitem_id_y() #1 {
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; HSA: define void @use_workitem_id_x() #1 {
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define void @use_workitem_id_x() #1 {
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%val = call i32 @llvm.amdgcn.workitem.id.x()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workitem_id_y() #2 {
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define void @use_workitem_id_y() #1 {
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%val = call i32 @llvm.amdgcn.workitem.id.y()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workitem_id_z() #2 {
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; HSA: define void @use_workitem_id_z() #3 {
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define void @use_workitem_id_z() #1 {
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%val = call i32 @llvm.amdgcn.workitem.id.z()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workgroup_id_y() #3 {
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; HSA: define void @use_workgroup_id_x() #4 {
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define void @use_workgroup_id_x() #1 {
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%val = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workgroup_id_y() #5 {
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define void @use_workgroup_id_y() #1 {
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%val = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workgroup_id_z() #4 {
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; HSA: define void @use_workgroup_id_z() #6 {
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define void @use_workgroup_id_z() #1 {
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%val = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_dispatch_ptr() #5 {
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; HSA: define void @use_dispatch_ptr() #7 {
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define void @use_dispatch_ptr() #1 {
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%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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store volatile i8 addrspace(2)* %dispatch.ptr, i8 addrspace(2)* addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_queue_ptr() #6 {
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; HSA: define void @use_queue_ptr() #8 {
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define void @use_queue_ptr() #1 {
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%queue.ptr = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()
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store volatile i8 addrspace(2)* %queue.ptr, i8 addrspace(2)* addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_dispatch_id() #7 {
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; HSA: define void @use_dispatch_id() #9 {
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define void @use_dispatch_id() #1 {
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%val = call i64 @llvm.amdgcn.dispatch.id()
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store volatile i64 %val, i64 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workgroup_id_y_workgroup_id_z() #8 {
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; HSA: define void @use_workgroup_id_y_workgroup_id_z() #10 {
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define void @use_workgroup_id_y_workgroup_id_z() #1 {
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%val0 = call i32 @llvm.amdgcn.workgroup.id.y()
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%val1 = call i32 @llvm.amdgcn.workgroup.id.z()
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@ -70,67 +86,91 @@ define void @use_workgroup_id_y_workgroup_id_z() #1 {
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ret void
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}
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; HSA: define void @func_indirect_use_workitem_id_y() #1 {
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; HSA: define void @func_indirect_use_workitem_id_x() #1 {
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define void @func_indirect_use_workitem_id_x() #1 {
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call void @use_workitem_id_x()
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ret void
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}
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; HSA: define void @kernel_indirect_use_workitem_id_x() #1 {
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define void @kernel_indirect_use_workitem_id_x() #1 {
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call void @use_workitem_id_x()
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ret void
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}
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; HSA: define void @func_indirect_use_workitem_id_y() #2 {
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define void @func_indirect_use_workitem_id_y() #1 {
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call void @use_workitem_id_y()
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ret void
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}
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; HSA: define void @func_indirect_use_workitem_id_z() #2 {
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; HSA: define void @func_indirect_use_workitem_id_z() #3 {
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define void @func_indirect_use_workitem_id_z() #1 {
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call void @use_workitem_id_z()
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ret void
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}
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; HSA: define void @func_indirect_use_workgroup_id_y() #3 {
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; HSA: define void @func_indirect_use_workgroup_id_x() #4 {
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define void @func_indirect_use_workgroup_id_x() #1 {
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call void @use_workgroup_id_x()
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ret void
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}
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; HSA: define void @kernel_indirect_use_workgroup_id_x() #4 {
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define void @kernel_indirect_use_workgroup_id_x() #1 {
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call void @use_workgroup_id_x()
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ret void
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}
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; HSA: define void @func_indirect_use_workgroup_id_y() #5 {
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define void @func_indirect_use_workgroup_id_y() #1 {
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call void @use_workgroup_id_y()
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ret void
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}
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; HSA: define void @func_indirect_use_workgroup_id_z() #4 {
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; HSA: define void @func_indirect_use_workgroup_id_z() #6 {
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define void @func_indirect_use_workgroup_id_z() #1 {
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call void @use_workgroup_id_z()
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ret void
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}
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; HSA: define void @func_indirect_indirect_use_workgroup_id_y() #3 {
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; HSA: define void @func_indirect_indirect_use_workgroup_id_y() #5 {
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define void @func_indirect_indirect_use_workgroup_id_y() #1 {
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call void @func_indirect_use_workgroup_id_y()
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ret void
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}
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; HSA: define void @indirect_x2_use_workgroup_id_y() #3 {
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; HSA: define void @indirect_x2_use_workgroup_id_y() #5 {
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define void @indirect_x2_use_workgroup_id_y() #1 {
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call void @func_indirect_indirect_use_workgroup_id_y()
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ret void
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}
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; HSA: define void @func_indirect_use_dispatch_ptr() #5 {
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; HSA: define void @func_indirect_use_dispatch_ptr() #7 {
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define void @func_indirect_use_dispatch_ptr() #1 {
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call void @use_dispatch_ptr()
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ret void
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}
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; HSA: define void @func_indirect_use_queue_ptr() #6 {
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; HSA: define void @func_indirect_use_queue_ptr() #8 {
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define void @func_indirect_use_queue_ptr() #1 {
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call void @use_queue_ptr()
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ret void
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}
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; HSA: define void @func_indirect_use_dispatch_id() #7 {
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; HSA: define void @func_indirect_use_dispatch_id() #9 {
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define void @func_indirect_use_dispatch_id() #1 {
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call void @use_dispatch_id()
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ret void
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}
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; HSA: define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #9 {
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; HSA: define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #11 {
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define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #1 {
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call void @func_indirect_use_workgroup_id_y_workgroup_id_z()
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ret void
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}
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; HSA: define void @recursive_use_workitem_id_y() #1 {
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; HSA: define void @recursive_use_workitem_id_y() #2 {
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define void @recursive_use_workitem_id_y() #1 {
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%val = call i32 @llvm.amdgcn.workitem.id.y()
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store volatile i32 %val, i32 addrspace(1)* undef
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@ -138,27 +178,27 @@ define void @recursive_use_workitem_id_y() #1 {
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ret void
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}
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; HSA: define void @call_recursive_use_workitem_id_y() #1 {
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; HSA: define void @call_recursive_use_workitem_id_y() #2 {
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define void @call_recursive_use_workitem_id_y() #1 {
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call void @recursive_use_workitem_id_y()
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ret void
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}
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; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #6 {
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; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #8 {
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define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
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%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
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store volatile i32 0, i32 addrspace(4)* %stof
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ret void
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}
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; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #10 {
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; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #12 {
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define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 {
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%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
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store volatile i32 0, i32 addrspace(4)* %stof
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ret void
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}
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; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #11 {
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; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #13 {
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define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 {
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%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
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store volatile i32 0, i32 addrspace(4)* %stof
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@ -166,45 +206,45 @@ define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %p
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|||
ret void
|
||||
}
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||||
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast() #6 {
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||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast() #8 {
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||||
define void @indirect_use_group_to_flat_addrspacecast() #1 {
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||||
call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null)
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast_gfx9() #9 {
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast_gfx9() #11 {
|
||||
define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 {
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||||
call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null)
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #6 {
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #8 {
|
||||
define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 {
|
||||
call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null)
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @use_kernarg_segment_ptr() #12 {
|
||||
; HSA: define void @use_kernarg_segment_ptr() #14 {
|
||||
define void @use_kernarg_segment_ptr() #1 {
|
||||
%kernarg.segment.ptr = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr()
|
||||
store volatile i8 addrspace(2)* %kernarg.segment.ptr, i8 addrspace(2)* addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @func_indirect_use_kernarg_segment_ptr() #12 {
|
||||
; HSA: define void @func_indirect_use_kernarg_segment_ptr() #14 {
|
||||
define void @func_indirect_use_kernarg_segment_ptr() #1 {
|
||||
call void @use_kernarg_segment_ptr()
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @use_implicitarg_ptr() #12 {
|
||||
; HSA: define void @use_implicitarg_ptr() #14 {
|
||||
define void @use_implicitarg_ptr() #1 {
|
||||
%implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr()
|
||||
store volatile i8 addrspace(2)* %implicitarg.ptr, i8 addrspace(2)* addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @func_indirect_use_implicitarg_ptr() #12 {
|
||||
; HSA: define void @func_indirect_use_implicitarg_ptr() #14 {
|
||||
define void @func_indirect_use_implicitarg_ptr() #1 {
|
||||
call void @use_implicitarg_ptr()
|
||||
ret void
|
||||
|
|
@ -215,15 +255,17 @@ attributes #1 = { nounwind "target-cpu"="fiji" }
|
|||
attributes #2 = { nounwind "target-cpu"="gfx900" }
|
||||
|
||||
; HSA: attributes #0 = { nounwind readnone speculatable }
|
||||
; HSA: attributes #1 = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" }
|
||||
; HSA: attributes #2 = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-y" "target-cpu"="fiji" }
|
||||
; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #5 = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" }
|
||||
; HSA: attributes #6 = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" }
|
||||
; HSA: attributes #7 = { nounwind "amdgpu-dispatch-id" "target-cpu"="fiji" }
|
||||
; HSA: attributes #8 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #9 = { nounwind "target-cpu"="fiji" }
|
||||
; HSA: attributes #10 = { nounwind "target-cpu"="gfx900" }
|
||||
; HSA: attributes #11 = { nounwind "amdgpu-queue-ptr" "target-cpu"="gfx900" }
|
||||
; HSA: attributes #12 = { nounwind "amdgpu-kernarg-segment-ptr" "target-cpu"="fiji" }
|
||||
; HSA: attributes #1 = { nounwind "amdgpu-work-item-id-x" "target-cpu"="fiji" }
|
||||
; HSA: attributes #2 = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" }
|
||||
; HSA: attributes #3 = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-x" "target-cpu"="fiji" }
|
||||
; HSA: attributes #5 = { nounwind "amdgpu-work-group-id-y" "target-cpu"="fiji" }
|
||||
; HSA: attributes #6 = { nounwind "amdgpu-work-group-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #7 = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" }
|
||||
; HSA: attributes #8 = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" }
|
||||
; HSA: attributes #9 = { nounwind "amdgpu-dispatch-id" "target-cpu"="fiji" }
|
||||
; HSA: attributes #10 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #11 = { nounwind "target-cpu"="fiji" }
|
||||
; HSA: attributes #12 = { nounwind "target-cpu"="gfx900" }
|
||||
; HSA: attributes #13 = { nounwind "amdgpu-queue-ptr" "target-cpu"="gfx900" }
|
||||
; HSA: attributes #14 = { nounwind "amdgpu-kernarg-segment-ptr" "target-cpu"="fiji" }
|
||||
|
|
|
|||
Loading…
Reference in New Issue