forked from OSchip/llvm-project
AMDGPU/GlobalISel: Custom lower control flow intrinsics
Replace the brcond for the 2 cases that act as branches. For now follow how the current system works, although I think we can eventually get rid of the pseudos. llvm-svn: 364832
This commit is contained in:
Matt Arsenault
parent
4073b33786
commit
e15770aec4
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@ -1046,3 +1046,67 @@ bool AMDGPULegalizerInfo::legalizeITOFP(
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MI.eraseFromParent();
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return true;
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}
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// Return the use branch instruction, otherwise null if the usage is invalid.
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static MachineInstr *verifyCFIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI) {
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Register CondDef = MI.getOperand(0).getReg();
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if (!MRI.hasOneNonDBGUse(CondDef))
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return nullptr;
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MachineInstr &UseMI = *MRI.use_instr_nodbg_begin(CondDef);
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return UseMI.getParent() == MI.getParent() &&
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UseMI.getOpcode() == AMDGPU::G_BRCOND ? &UseMI : nullptr;
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}
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bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const {
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// Replace the use G_BRCOND with the exec manipulate and branch pseudos.
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switch (MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID()) {
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case Intrinsic::amdgcn_if: {
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if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI)) {
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const SIRegisterInfo *TRI
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= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
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B.setInstr(*BrCond);
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Register Def = MI.getOperand(1).getReg();
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Register Use = MI.getOperand(3).getReg();
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B.buildInstr(AMDGPU::SI_IF)
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.addDef(Def)
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.addUse(Use)
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.addMBB(BrCond->getOperand(1).getMBB());
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MRI.setRegClass(Def, TRI->getWaveMaskRegClass());
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MRI.setRegClass(Use, TRI->getWaveMaskRegClass());
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MI.eraseFromParent();
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BrCond->eraseFromParent();
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return true;
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}
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return false;
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}
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case Intrinsic::amdgcn_loop: {
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if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI)) {
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const SIRegisterInfo *TRI
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= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
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B.setInstr(*BrCond);
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Register Reg = MI.getOperand(2).getReg();
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B.buildInstr(AMDGPU::SI_LOOP)
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.addUse(Reg)
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.addMBB(BrCond->getOperand(1).getMBB());
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MI.eraseFromParent();
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BrCond->eraseFromParent();
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MRI.setRegClass(Reg, TRI->getWaveMaskRegClass());
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return true;
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}
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return false;
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}
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default:
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return true;
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}
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return true;
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}
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@ -46,6 +46,10 @@ public:
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MachineIRBuilder &MIRBuilder) const;
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bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder, bool Signed) const;
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bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const override;
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};
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} // End llvm namespace.
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#endif
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@ -0,0 +1,73 @@
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s
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# Make sure incorrect usage of control flow intrinsics fails to select in case some transform separated the intrinsic from its branch.
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# ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_different_block)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_brcond_user)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_multi_user)
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# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_condition)
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---
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name: brcond_si_if_different_block
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body: |
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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bb.1:
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G_BRCOND %3, %bb.1
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...
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---
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name: si_if_not_brcond_user
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s32) = G_SELECT %3, %0, %1
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S_ENDPGM 0, implicit %5
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...
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---
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name: si_if_multi_user
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s32) = G_SELECT %3, %0, %1
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G_BRCOND %3, %bb.1
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bb.1:
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S_ENDPGM 0, implicit %5
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...
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---
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name: si_if_not_condition
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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%5:_(s1) = G_CONSTANT i1 true
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%6:_(s1) = G_XOR %3, %5
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G_BRCOND %6, %bb.1
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bb.1:
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...
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@ -1,18 +1,27 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s
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---
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name: legal_brcond
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name: legal_brcond_vcc
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body: |
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; CHECK-LABEL: name: legal_brcond
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
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; CHECK: bb.1:
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bb.0.entry:
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; WAVE64-LABEL: name: legal_brcond_vcc
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; WAVE64: bb.0:
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; WAVE64: successors: %bb.1(0x80000000)
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; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE64: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE64: G_BRCOND [[ICMP]](s1), %bb.1
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; WAVE64: bb.1:
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; WAVE32-LABEL: name: legal_brcond_vcc
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; WAVE32: bb.0:
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; WAVE32: successors: %bb.1(0x80000000)
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; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE32: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE32: G_BRCOND [[ICMP]](s1), %bb.1
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; WAVE32: bb.1:
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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@ -22,3 +31,98 @@ body: |
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bb.1:
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...
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---
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name: legal_brcond_scc
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body: |
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; WAVE64-LABEL: name: legal_brcond_scc
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; WAVE64: bb.0:
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; WAVE64: successors: %bb.1(0x80000000)
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; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; WAVE64: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
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; WAVE64: G_BRCOND [[ICMP]](s1), %bb.1
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; WAVE64: bb.1:
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; WAVE32-LABEL: name: legal_brcond_scc
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; WAVE32: bb.0:
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; WAVE32: successors: %bb.1(0x80000000)
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; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; WAVE32: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
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; WAVE32: G_BRCOND [[ICMP]](s1), %bb.1
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; WAVE32: bb.1:
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bb.0:
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liveins: $sgpr0, $sgpr1
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:scc(s1) = G_ICMP intpred(eq), %0, %1
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G_BRCOND %2, %bb.1
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bb.1:
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...
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---
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name: brcond_si_if
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body: |
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; WAVE64-LABEL: name: brcond_si_if
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; WAVE64: bb.0:
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; WAVE64: successors: %bb.1(0x80000000)
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; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE64: bb.1:
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; WAVE32-LABEL: name: brcond_si_if
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; WAVE32: bb.0:
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; WAVE32: successors: %bb.1(0x80000000)
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; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
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; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE32: bb.1:
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
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G_BRCOND %3, %bb.1
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bb.1:
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...
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---
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name: brcond_si_loop
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body: |
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; WAVE64-LABEL: name: brcond_si_loop
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; WAVE64: bb.0:
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; WAVE64: successors: %bb.1(0x80000000)
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; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
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; WAVE64: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE64: bb.1:
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; WAVE32-LABEL: name: brcond_si_loop
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; WAVE32: bb.0:
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; WAVE32: successors: %bb.1(0x80000000)
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; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
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; WAVE32: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
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; WAVE32: bb.1:
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bb.0:
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successors: %bb.1
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liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s64) = COPY $sgpr0_sgpr1
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%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
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G_BRCOND %3, %bb.1
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bb.1:
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...
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