forked from OSchip/llvm-project
[X86][XOP] Add missing scheduler classes to XOP instructions
All match equivalent basic classes (WritePHAdd, WriteFAdd etc.) according to both the AMD 15h SOG and Agner's tables. llvm-svn: 318758
This commit is contained in:
Simon Pilgrim
parent
9caefe364a
commit
e1490afa4c
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@ -14,10 +14,11 @@
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multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP;
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[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[WritePHAdd]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
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[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
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Sched<[WritePHAdd, ReadAfterLd]>;
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}
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let ExeDomain = SSEPackedInt in {
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@ -43,30 +44,33 @@ multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
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Operand memop, ComplexPattern mem_cpat> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP;
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[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[WriteFAdd]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
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[(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP,
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Sched<[WriteFAdd, ReadAfterLd]>;
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}
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multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
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PatFrag memop> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP;
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[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[WriteFAdd]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
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[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
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Sched<[WriteFAdd, ReadAfterLd]>;
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}
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multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
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PatFrag memop> {
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def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L;
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[(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L, Sched<[WriteFAdd]>;
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def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
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[(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L,
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Sched<[WriteFAdd, ReadAfterLd]>;
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}
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let ExeDomain = SSEPackedSingle in {
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@ -135,12 +139,14 @@ multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(ins VR128:$src1, u8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
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(vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>,
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XOP, Sched<[WriteVecShift]>;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src1, u8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
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(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>,
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XOP, Sched<[WriteVecShift, ReadAfterLd]>;
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}
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let ExeDomain = SSEPackedInt in {
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@ -158,14 +164,15 @@ multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V;
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V,
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Sched<[WriteVecIMul]>;
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def rm : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
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VR128:$src3))]>, XOP_4V;
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VR128:$src3))]>, XOP_4V, Sched<[WriteVecIMul, ReadAfterLd]>;
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}
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let ExeDomain = SSEPackedInt in {
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@ -214,7 +221,7 @@ multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128>
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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imm:$cc)))]>,
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XOP_4V;
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XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
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!strconcat("vpcom${cc}", Suffix,
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@ -223,19 +230,19 @@ multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128>
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(vt128 (OpNode (vt128 VR128:$src1),
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(vt128 (bitconvert (loadv2i64 addr:$src2))),
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imm:$cc)))]>,
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XOP_4V;
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XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
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let isAsmParserOnly = 1, hasSideEffects = 0 in {
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def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, u8imm:$src3),
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!strconcat("vpcom", Suffix,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V;
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[]>, XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
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let mayLoad = 1 in
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def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
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!strconcat("vpcom", Suffix,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V;
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[]>, XOP_4V, Sched<[WriteVecALU, ReadAfterLd]>;
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}
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}
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@ -259,7 +266,7 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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(vt128 VR128:$src3))))]>,
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XOP_4V;
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XOP_4V, Sched<[WriteShuffle]>;
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def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i128mem:$src3),
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!strconcat(OpcodeStr,
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@ -267,7 +274,7 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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(vt128 (bitconvert (loadv2i64 addr:$src3))))))]>,
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XOP_4V, VEX_W;
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XOP_4V, VEX_W, Sched<[WriteShuffle, ReadAfterLd]>;
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def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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@ -275,14 +282,14 @@ multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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[(set VR128:$dst,
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(v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))),
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(vt128 VR128:$src3))))]>,
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XOP_4V;
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XOP_4V, Sched<[WriteShuffle, ReadAfterLd]>;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, VEX_W, FoldGenData<NAME#rrr>;
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[]>, XOP_4V, VEX_W, Sched<[WriteShuffle]>, FoldGenData<NAME#rrr>;
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}
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let ExeDomain = SSEPackedInt in {
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@ -297,28 +304,29 @@ multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
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(X86andnp RC:$src3, RC:$src2))))]>, XOP_4V;
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(X86andnp RC:$src3, RC:$src2))))]>, XOP_4V,
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Sched<[WriteShuffle]>;
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def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (VT (or (and (load addr:$src3), RC:$src1),
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(X86andnp (load addr:$src3), RC:$src2))))]>,
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XOP_4V, VEX_W;
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XOP_4V, VEX_W, Sched<[WriteShuffle, ReadAfterLd]>;
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def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
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(X86andnp RC:$src3, (load addr:$src2)))))]>,
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XOP_4V;
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XOP_4V, Sched<[WriteShuffle, ReadAfterLd]>;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, VEX_W, FoldGenData<NAME#rrr>;
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[]>, XOP_4V, VEX_W, Sched<[WriteShuffle]>, FoldGenData<NAME#rrr>;
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}
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let ExeDomain = SSEPackedInt in {
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@ -335,7 +343,8 @@ multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set RC:$dst,
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(VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 imm:$src4))))]>;
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(VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 imm:$src4))))]>,
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Sched<[WriteFShuffle]>;
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def rm : IXOP5<Opc, MRMSrcMemOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, intmemop:$src3, u8imm:$src4),
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!strconcat(OpcodeStr,
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@ -343,21 +352,23 @@ multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
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[(set RC:$dst,
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(VT (X86vpermil2 RC:$src1, RC:$src2,
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(bitconvert (IntLdFrag addr:$src3)),
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(i8 imm:$src4))))]>, VEX_W;
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(i8 imm:$src4))))]>, VEX_W,
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Sched<[WriteFShuffle, ReadAfterLd]>;
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def mr : IXOP5<Opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, fpmemop:$src2, RC:$src3, u8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set RC:$dst,
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(VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2),
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RC:$src3, (i8 imm:$src4))))]>;
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RC:$src3, (i8 imm:$src4))))]>,
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Sched<[WriteFShuffle, ReadAfterLd]>;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rr_REV : IXOP5<Opc, MRMSrcRegOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>, VEX_W, FoldGenData<NAME#rr>;
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[]>, VEX_W, Sched<[WriteFShuffle]>, FoldGenData<NAME#rr>;
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}
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let ExeDomain = SSEPackedDouble in {
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