From e135ffd55416a98a634621b99584ece0c19e8003 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 25 Sep 2015 21:41:28 +0000 Subject: [PATCH] AMDGPU/SI: Use .hsatext section instead of .text for HSA Reviewers: arsenm, grosbach, rafael Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12424 llvm-svn: 248619 --- .../AMDGPU/AMDGPUHSATargetObjectFile.cpp | 35 ++++++++++++++++ .../Target/AMDGPU/AMDGPUHSATargetObjectFile.h | 35 ++++++++++++++++ .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 14 +++++-- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 4 +- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 10 +++++ llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 + .../AMDGPU/MCTargetDesc/AMDGPUELFStreamer.cpp | 26 ++++++++++++ .../AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h | 40 +++++++++++++++++++ .../AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp | 5 +++ .../AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h | 1 + .../MCTargetDesc/AMDGPUMCTargetDesc.cpp | 11 +++++ .../MCTargetDesc/AMDGPUTargetStreamer.cpp | 6 ++- .../Target/AMDGPU/MCTargetDesc/CMakeLists.txt | 1 + .../Target/AMDGPU/MCTargetDesc/LLVMBuild.txt | 2 +- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 10 +++++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 3 ++ llvm/lib/Target/AMDGPU/Utils/LLVMBuild.txt | 2 +- llvm/test/CodeGen/AMDGPU/hsa.ll | 13 ++++++ llvm/test/MC/AMDGPU/hsa-text.s | 34 ++++++++++++++++ llvm/test/MC/AMDGPU/hsa.s | 15 ++++++- 20 files changed, 258 insertions(+), 10 deletions(-) create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.cpp create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.h create mode 100644 llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.cpp create mode 100644 llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h create mode 100644 llvm/test/MC/AMDGPU/hsa-text.s diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.cpp new file mode 100644 index 000000000000..fa54f4a017cb --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.cpp @@ -0,0 +1,35 @@ +//===-- AMDGPUHSATargetObjectFile.cpp - AMDGPU Object Files ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUHSATargetObjectFile.h" +#include "Utils/AMDGPUBaseInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/Support/ELF.h" + +using namespace llvm; + +void AMDGPUHSATargetObjectFile::Initialize(MCContext &Ctx, + const TargetMachine &TM){ + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + InitializeELF(TM.Options.UseInitArray); + + TextSection = AMDGPU::getHSATextSection(Ctx); + +} + +MCSection *AMDGPUHSATargetObjectFile::SelectSectionForGlobal( + const GlobalValue *GV, SectionKind Kind, + Mangler &Mang, + const TargetMachine &TM) const { + if (Kind.isText() && !GV->hasComdat()) + return getTextSection(); + + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang, TM); +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.h b/llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.h new file mode 100644 index 000000000000..d13aba56cdd7 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUHSATargetObjectFile.h @@ -0,0 +1,35 @@ +//===-- AMDGPUHSATargetObjectFile.h - AMDGPU HSA Object Info ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file declares the AMDGPU-specific subclass of +/// TargetLoweringObjectFile use for targeting the HSA-runtime. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUHSATARGETOBJECTFILE_H +#define LLVM_LIB_TARGET_AMDGPU_AMDGPUHSATARGETOBJECTFILE_H + +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + +class AMDGPUHSATargetObjectFile final : public TargetLoweringObjectFileELF { +public: + void Initialize(MCContext &Ctx, const TargetMachine &TM); + + MCSection *SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, + Mangler &Mang, + const TargetMachine &TM) const override; +}; + +} // end namespace llvm + +#endif diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f8fc3bea9ff1..25a395941e9f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// #include "AMDGPUTargetMachine.h" +#include "AMDGPUHSATargetObjectFile.h" #include "AMDGPU.h" #include "AMDGPUTargetTransformInfo.h" #include "R600ISelLowering.h" @@ -43,6 +44,13 @@ extern "C" void LLVMInitializeAMDGPUTarget() { RegisterTargetMachine Y(TheGCNTarget); } +static std::unique_ptr createTLOF(const Triple &TT) { + if (TT.getOS() == Triple::AMDHSA) + return make_unique(); + + return make_unique(); +} + static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) { return new ScheduleDAGMILive(C, make_unique()); } @@ -72,15 +80,13 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OptLevel) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, OptLevel), - TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this), + TLOF(createTLOF(getTargetTriple())), Subtarget(TT, CPU, FS, *this), IntrinsicInfo() { setRequiresStructuredCFG(true); initAsmInfo(); } -AMDGPUTargetMachine::~AMDGPUTargetMachine() { - delete TLOF; -} +AMDGPUTargetMachine::~AMDGPUTargetMachine() { } //===----------------------------------------------------------------------===// // R600 Target Machine (R600 -> Cayman) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 14792e347a7a..236e3f824030 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -32,7 +32,7 @@ class AMDGPUTargetMachine : public LLVMTargetMachine { private: protected: - TargetLoweringObjectFile *TLOF; + std::unique_ptr TLOF; AMDGPUSubtarget Subtarget; AMDGPUIntrinsicInfo IntrinsicInfo; @@ -52,7 +52,7 @@ public: TargetIRAnalysis getTargetIRAnalysis() override; TargetLoweringObjectFile *getObjFileLowering() const override { - return TLOF; + return TLOF.get(); } }; diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index de1ea0b7f448..c74d16d43860 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -344,6 +344,7 @@ private: bool ParseDirectiveHSACodeObjectISA(); bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header); bool ParseDirectiveAMDKernelCodeT(); + bool ParseSectionDirectiveHSAText(); public: AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser, @@ -903,6 +904,12 @@ bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() { return false; } +bool AMDGPUAsmParser::ParseSectionDirectiveHSAText() { + getParser().getStreamer().SwitchSection( + AMDGPU::getHSATextSection(getContext())); + return false; +} + bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { StringRef IDVal = DirectiveID.getString(); @@ -915,6 +922,9 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { if (IDVal == ".amd_kernel_code_t") return ParseDirectiveAMDKernelCodeT(); + if (IDVal == ".hsatext" || IDVal == ".text") + return ParseSectionDirectiveHSAText(); + return true; } diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index dd6db61fb30d..e8780b7cbeca 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -17,6 +17,7 @@ add_llvm_target(AMDGPUCodeGen AMDGPUAlwaysInlinePass.cpp AMDGPUAsmPrinter.cpp AMDGPUFrameLowering.cpp + AMDGPUHSATargetObjectFile.cpp AMDGPUIntrinsicInfo.cpp AMDGPUISelDAGToDAG.cpp AMDGPUMCInstLower.cpp diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.cpp new file mode 100644 index 000000000000..9ff9fe794d2b --- /dev/null +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.cpp @@ -0,0 +1,26 @@ +//===-------- AMDGPUELFStreamer.cpp - ELF Object Output -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUELFStreamer.h" +#include "Utils/AMDGPUBaseInfo.h" + +using namespace llvm; + +void AMDGPUELFStreamer::InitSections(bool NoExecStack) { + // Start with the .hsatext section by default. + SwitchSection(AMDGPU::getHSATextSection(getContext())); +} + +MCELFStreamer *llvm::createAMDGPUELFStreamer(MCContext &Context, + MCAsmBackend &MAB, + raw_pwrite_stream &OS, + MCCodeEmitter *Emitter, + bool RelaxAll) { + return new AMDGPUELFStreamer(Context, MAB, OS, Emitter); +} diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h new file mode 100644 index 000000000000..488d7e74d741 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h @@ -0,0 +1,40 @@ +//===-------- AMDGPUELFStreamer.h - ELF Object Output ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is a custom MCELFStreamer which allows us to insert some hooks before +// emitting data into an actual object file. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUELFSTREAMER_H +#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUELFSTREAMER_H + +#include "llvm/MC/MCELFStreamer.h" + +namespace llvm { +class MCAsmBackend; +class MCCodeEmitter; +class MCContext; +class MCSubtargetInfo; + +class AMDGPUELFStreamer : public MCELFStreamer { +public: + AMDGPUELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, + MCCodeEmitter *Emitter) + : MCELFStreamer(Context, MAB, OS, Emitter) { } + + virtual void InitSections(bool NoExecStac) override; +}; + +MCELFStreamer *createAMDGPUELFStreamer(MCContext &Context, MCAsmBackend &MAB, + raw_pwrite_stream &OS, + MCCodeEmitter *Emitter, bool RelaxAll); +} // namespace llvm. + +#endif diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp index 028a86dfc7ad..d79ffdf52a74 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp @@ -41,3 +41,8 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() { //===--- Dwarf Emission Directives -----------------------------------===// SupportsDebugInformation = true; } + +bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const { + return SectionName == ".hsatext" || + MCAsmInfo::shouldOmitSectionDirective(SectionName); +} diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h index 119dd425916e..a546961705d7 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h @@ -27,6 +27,7 @@ class Triple; class AMDGPUMCAsmInfo : public MCAsmInfoELF { public: explicit AMDGPUMCAsmInfo(const Triple &TT); + bool shouldOmitSectionDirective(StringRef SectionName) const override; }; } // namespace llvm #endif diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp index c709741f3777..f70409470276 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "AMDGPUMCTargetDesc.h" +#include "AMDGPUELFStreamer.h" #include "AMDGPUMCAsmInfo.h" #include "AMDGPUTargetStreamer.h" #include "InstPrinter/AMDGPUInstPrinter.h" @@ -85,6 +86,15 @@ static MCTargetStreamer * createAMDGPUObjectTargetStreamer( return new AMDGPUTargetELFStreamer(S); } +static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, + MCAsmBackend &MAB, raw_pwrite_stream &OS, + MCCodeEmitter *Emitter, bool RelaxAll) { + if (T.getOS() == Triple::AMDHSA) + return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll); + + return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll); +} + extern "C" void LLVMInitializeAMDGPUTargetMC() { for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) { RegisterMCAsmInfo X(*T); @@ -95,6 +105,7 @@ extern "C" void LLVMInitializeAMDGPUTargetMC() { TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo); TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter); TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend); + TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); } // R600 specific registration diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp index 09e6cb1f1ffc..135ac7b821bf 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -13,6 +13,7 @@ #include "AMDGPUTargetStreamer.h" #include "SIDefines.h" +#include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFStreamer.h" @@ -291,7 +292,10 @@ AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { MCStreamer &OS = getStreamer(); OS.PushSection(); - OS.SwitchSection(OS.getContext().getObjectFileInfo()->getTextSection()); + // The MCObjectFileInfo that is available to the assembler is a generic + // implementation and not AMDGPUHSATargetObjectFile, so we can't use + // MCObjectFileInfo::getTextSection() here for fetching the HSATextSection. + OS.SwitchSection(AMDGPU::getHSATextSection(OS.getContext())); OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header))); OS.PopSection(); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt index 8306a051ff98..c823ee7e0080 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ add_llvm_library(LLVMAMDGPUDesc AMDGPUAsmBackend.cpp AMDGPUELFObjectWriter.cpp + AMDGPUELFStreamer.cpp AMDGPUMCCodeEmitter.cpp AMDGPUMCTargetDesc.cpp AMDGPUMCAsmInfo.cpp diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/LLVMBuild.txt b/llvm/lib/Target/AMDGPU/MCTargetDesc/LLVMBuild.txt index 4217bb362975..aa9a02198d04 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/LLVMBuild.txt +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = AMDGPUDesc parent = AMDGPU -required_libraries = MC AMDGPUAsmPrinter AMDGPUInfo Support +required_libraries = MC AMDGPUAsmPrinter AMDGPUInfo AMDGPUUtils Support add_to_library_groups = AMDGPU diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index b76b4007003f..e70f79d5a7be 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -7,6 +7,8 @@ // //===----------------------------------------------------------------------===// #include "AMDGPUBaseInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSectionELF.h" #include "llvm/MC/SubtargetFeature.h" #define GET_SUBTARGETINFO_ENUM @@ -56,5 +58,13 @@ void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, Header.private_segment_alignment = 4; } +MCSection *getHSATextSection(MCContext &Ctx) { + return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC | ELF::SHF_WRITE | + ELF::SHF_EXECINSTR | + ELF::SHF_AMDGPU_HSA_AGENT | + ELF::SHF_AMDGPU_HSA_CODE); +} + } // End namespace AMDGPU } // End namespace llvm diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index f57028cc5bfd..59a32a6b592d 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -15,6 +15,8 @@ namespace llvm { class FeatureBitset; +class MCContext; +class MCSection; namespace AMDGPU { @@ -27,6 +29,7 @@ struct IsaVersion { IsaVersion getIsaVersion(const FeatureBitset &Features); void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const FeatureBitset &Features); +MCSection *getHSATextSection(MCContext &Ctx); } // end namespace AMDGPU } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/Utils/LLVMBuild.txt b/llvm/lib/Target/AMDGPU/Utils/LLVMBuild.txt index dec5360e3bc7..f8d78165d9e3 100644 --- a/llvm/lib/Target/AMDGPU/Utils/LLVMBuild.txt +++ b/llvm/lib/Target/AMDGPU/Utils/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = AMDGPUUtils parent = AMDGPU -required_libraries = Support +required_libraries = MC Support add_to_library_groups = AMDGPU diff --git a/llvm/test/CodeGen/AMDGPU/hsa.ll b/llvm/test/CodeGen/AMDGPU/hsa.ll index 653a6bb1b609..5c7498293817 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa.ll @@ -6,6 +6,17 @@ ; The SHT_NOTE section contains the output from the .hsa_code_object_* ; directives. +; ELF: Section { +; ELF: Name: .hsatext +; ELF: Type: SHT_PROGBITS (0x1) +; ELF: Flags [ (0xC00007) +; ELF: SHF_ALLOC (0x2) +; ELF: SHF_AMDGPU_HSA_AGENT (0x800000) +; ELF: SHF_AMDGPU_HSA_CODE (0x400000) +; ELF: SHF_EXECINSTR (0x4) +; ELF: SHF_WRITE (0x1) +; ELF: } + ; ELF: SHT_NOTE ; ELF: 0000: 04000000 08000000 01000000 414D4400 ; ELF: 0010: 01000000 00000000 04000000 1B000000 @@ -17,6 +28,8 @@ ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" +; HSA: .hsatext + ; HSA: {{^}}simple: ; HSA: .amd_kernel_code_t ; HSA: .end_amd_kernel_code_t diff --git a/llvm/test/MC/AMDGPU/hsa-text.s b/llvm/test/MC/AMDGPU/hsa-text.s new file mode 100644 index 000000000000..1d2f1f1619e1 --- /dev/null +++ b/llvm/test/MC/AMDGPU/hsa-text.s @@ -0,0 +1,34 @@ +// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM +// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF + +// For compatibility reasons we treat convert .text sections to .hsatext + +// ELF: Section { + +// We want to avoid emitting an empty .text section. +// ELF-NOT: Name: .text + +// ELF: Name: .hsatext +// ELF: Type: SHT_PROGBITS (0x1) +// ELF: Flags [ (0xC00007) +// ELF: SHF_ALLOC (0x2) +// ELF: SHF_AMDGPU_HSA_AGENT (0x800000) +// ELF: SHF_AMDGPU_HSA_CODE (0x400000) +// ELF: SHF_EXECINSTR (0x4) +// ELF: SHF_WRITE (0x1) +// ELF: Size: 260 +// ELF: } + +.hsa_code_object_version 1,0 +// ASM: .hsa_code_object_version 1,0 + +.hsa_code_object_isa 7,0,0,"AMD","AMDGPU" +// ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" + +.text +// ASM: .hsatext + +.amd_kernel_code_t +.end_amd_kernel_code_t + +s_endpgm diff --git a/llvm/test/MC/AMDGPU/hsa.s b/llvm/test/MC/AMDGPU/hsa.s index 7dfea0fe787e..ae50673492be 100644 --- a/llvm/test/MC/AMDGPU/hsa.s +++ b/llvm/test/MC/AMDGPU/hsa.s @@ -1,6 +1,17 @@ // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF +// ELF: Section { +// ELF: Name: .hsatext +// ELF: Type: SHT_PROGBITS (0x1) +// ELF: Flags [ (0xC00007) +// ELF: SHF_ALLOC (0x2) +// ELF: SHF_AMDGPU_HSA_AGENT (0x800000) +// ELF: SHF_AMDGPU_HSA_CODE (0x400000) +// ELF: SHF_EXECINSTR (0x4) +// ELF: SHF_WRITE (0x1) +// ELF: } + // ELF: SHT_NOTE // ELF: 0000: 04000000 08000000 01000000 414D4400 // ELF: 0010: 01000000 00000000 04000000 1B000000 @@ -14,7 +25,9 @@ .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" // ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" -.text +.hsatext +// ASM: .hsatext + amd_kernel_code_t_test_all: ; Test all amd_kernel_code_t members with non-default values. .amd_kernel_code_t