[CodeGenPrepare][X86] Add bitreverse detection tests

Initially only test for XOP which is the only thing that supports scalar bitreverse - we can add vector tests later.
2021-05-04 13:20:31 +01:00 · 2021-05-04 13:20:31 +01:00 · e0dd708f40
parent bd82cec016
commit e0dd708f40
1 changed files with 97 additions and 0 deletions
--- a/llvm/test/Transforms/CodeGenPrepare/X86/bitreverse-recognize.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/bitreverse-recognize.ll
@ -0,0 +1,97 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -loop-unroll -codegenprepare -S -mtriple=x86_64-- -mattr=+xop | FileCheck %s
+
+define i32 @bitreverse_i32(i32 %a) {
+; CHECK-LABEL: @bitreverse_i32(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[REV:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[A:%.*]])
+; CHECK-NEXT:    ret i32 [[REV]]
+;
+entry:
+  br label %for.body
+
+for.cond.cleanup:                                 ; preds = %for.body
+  ret i32 %or
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %b.07 = phi i32 [ 0, %entry ], [ %or, %for.body ]
+  %shr = lshr i32 %a, %i.08
+  %and = and i32 %shr, 1
+  %sub = sub nuw nsw i32 31, %i.08
+  %shl = shl i32 %and, %sub
+  %or = or i32 %shl, %b.07
+  %inc = add nuw nsw i32 %i.08, 1
+  %exitcond = icmp eq i32 %inc, 32
+  br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !3
+}
+
+; PR40058
+define i64 @bitreverse_i64(i64 %0) {
+; CHECK-LABEL: @bitreverse_i64(
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr i64 [[TMP0:%.*]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and i64 [[TMP2]], 6148914691236517205
+; CHECK-NEXT:    [[TMP4:%.*]] = shl i64 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], -6148914691236517206
+; CHECK-NEXT:    [[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]
+; CHECK-NEXT:    [[TMP7:%.*]] = lshr i64 [[TMP6]], 2
+; CHECK-NEXT:    [[TMP8:%.*]] = and i64 [[TMP7]], 3689348814741910323
+; CHECK-NEXT:    [[TMP9:%.*]] = shl i64 [[TMP6]], 2
+; CHECK-NEXT:    [[TMP10:%.*]] = and i64 [[TMP9]], -3689348814741910324
+; CHECK-NEXT:    [[TMP11:%.*]] = or i64 [[TMP8]], [[TMP10]]
+; CHECK-NEXT:    [[TMP12:%.*]] = lshr i64 [[TMP11]], 4
+; CHECK-NEXT:    [[TMP13:%.*]] = and i64 [[TMP12]], 1085102592571150095
+; CHECK-NEXT:    [[TMP14:%.*]] = shl i64 [[TMP11]], 4
+; CHECK-NEXT:    [[TMP15:%.*]] = and i64 [[TMP14]], -1085102592571150096
+; CHECK-NEXT:    [[TMP16:%.*]] = or i64 [[TMP13]], [[TMP15]]
+; CHECK-NEXT:    [[TMP17:%.*]] = lshr i64 [[TMP16]], 8
+; CHECK-NEXT:    [[TMP18:%.*]] = and i64 [[TMP17]], 71777214294589695
+; CHECK-NEXT:    [[TMP19:%.*]] = shl i64 [[TMP16]], 8
+; CHECK-NEXT:    [[TMP20:%.*]] = and i64 [[TMP19]], -71777214294589696
+; CHECK-NEXT:    [[TMP21:%.*]] = or i64 [[TMP18]], [[TMP20]]
+; CHECK-NEXT:    [[TMP22:%.*]] = lshr i64 [[TMP21]], 16
+; CHECK-NEXT:    [[TMP23:%.*]] = and i64 [[TMP22]], 281470681808895
+; CHECK-NEXT:    [[TMP24:%.*]] = shl i64 [[TMP21]], 16
+; CHECK-NEXT:    [[TMP25:%.*]] = and i64 [[TMP24]], -281470681808896
+; CHECK-NEXT:    [[TMP26:%.*]] = or i64 [[TMP23]], [[TMP25]]
+; CHECK-NEXT:    [[TMP27:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[TMP26]], i64 [[TMP26]], i64 32)
+; CHECK-NEXT:    ret i64 [[TMP27]]
+;
+  %2 = lshr i64 %0, 1
+  %3 = and i64 %2, 6148914691236517205
+  %4 = shl i64 %0, 1
+  %5 = and i64 %4, -6148914691236517206
+  %6 = or i64 %3, %5
+  %7 = lshr i64 %6, 2
+  %8 = and i64 %7, 3689348814741910323
+  %9 = shl i64 %6, 2
+  %10 = and i64 %9, -3689348814741910324
+  %11 = or i64 %8, %10
+  %12 = lshr i64 %11, 4
+  %13 = and i64 %12, 1085102592571150095
+  %14 = shl i64 %11, 4
+  %15 = and i64 %14, -1085102592571150096
+  %16 = or i64 %13, %15
+  %17 = lshr i64 %16, 8
+  %18 = and i64 %17, 71777214294589695
+  %19 = shl i64 %16, 8
+  %20 = and i64 %19, -71777214294589696
+  %21 = or i64 %18, %20
+  %22 = lshr i64 %21, 16
+  %23 = and i64 %22, 281470681808895
+  %24 = shl i64 %21, 16
+  %25 = and i64 %24, -281470681808896
+  %26 = or i64 %23, %25
+  %27 = tail call i64 @llvm.fshl.i64(i64 %26, i64 %26, i64 32)
+  ret i64 %27
+}
+declare i64 @llvm.fshl.i64(i64, i64, i64)
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, !"min_enum_size", i32 4}
+!2 = !{!"clang version 3.8.0"}
+!3 = distinct !{!3, !4}
+!4 = !{!"llvm.loop.unroll.full"}