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Remove comment references to itineraries. NFCI. 

llvm-svn: 330021
This commit is contained in:
Simon Pilgrim 2018-04-13 14:31:57 +00:00
parent a9879fc3b6
commit e0c7868ded
3 changed files with 4 additions and 4 deletions
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2
llvm/lib/Target/X86/X86InstrMPX.td
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@ -13,7 +13,7 @@
//
//===----------------------------------------------------------------------===//
// FIXME: Investigate a better scheduler itinerary once MPX is used inside LLVM.
// FIXME: Investigate a better scheduler class once MPX is used inside LLVM.
let SchedRW = [WriteSystem] in {
multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {

2
llvm/lib/Target/X86/X86Schedule.td
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@ -183,7 +183,7 @@ def WriteNop : SchedWrite;
// latencies. Since these latencies are not used for pipeline hazards,
// they do not need to be exact.
//
// The GenericX86Model contains no instruction itineraries
// The GenericX86Model contains no instruction schedules
// and disables PostRAScheduler.
class GenericX86Model : SchedMachineModel {
let IssueWidth = 4;

4
llvm/lib/Target/X86/X86ScheduleZnver1.td
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@ -246,7 +246,7 @@ def : WriteRes<WriteNop, []>;
defm : ZnWriteResFpuPair<WriteFShuffle256, [ZnFPU], 100>;
defm : ZnWriteResFpuPair<WriteFVarShuffle256, [ZnFPU], 100>;
//Microcoded Instructions
// Microcoded Instructions
let Latency = 100 in {
def : WriteRes<WriteMicrocoded, []>;
def : WriteRes<WriteSystem, []>;
@ -264,7 +264,7 @@ let Latency = 100 in {
def : WriteRes<WritePCmpIStrILd, []>;
}
//=== Regex based itineraries ===//
//=== Regex based InstRW ===//
// Notation:
// - r: register.
// - m = memory.