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[Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc. 

llvm-svn: 202598
This commit is contained in:
Venkatraman Govindaraju 2014-03-01 18:54:52 +00:00
parent 2a9c430677
commit e0c5bff720
5 changed files with 36 additions and 7 deletions
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8
llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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@ -419,7 +419,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return Error(ErrorLoc, "invalid operand for instruction");
}
case Match_MnemonicFail:
return Error(IDLoc, "invalid instruction");
return Error(IDLoc, "invalid instruction mnemonic");
}
return true;
}
@ -448,11 +448,7 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands)
{
// Check if we have valid mnemonic.
if (!mnemonicIsValid(Name, 0)) {
Parser.eatToEndOfStatement();
return Error(NameLoc, "Unknown instruction");
}
// First operand in MCInst is instruction mnemonic.
Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));

3
llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
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@ -67,6 +67,9 @@ static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
Triple TheTriple(TT);
if (CPU.empty())
CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8";
InitSparcMCSubtargetInfo(X, TT, CPU, FS);
return X;
}

6
llvm/lib/Target/Sparc/SparcInstrAliases.td
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@ -143,3 +143,9 @@ def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
// restore -> restore %g0, %g0, %g0
def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;

3
llvm/lib/Target/Sparc/SparcInstrInfo.td
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@ -29,7 +29,8 @@ def Is64Bit : Predicate<"Subtarget.is64Bit()">;
// HasV9 - This predicate is true when the target processor supports V9
// instructions. Note that the machine may be running in 32-bit mode.
def HasV9 : Predicate<"Subtarget.isV9()">;
def HasV9 : Predicate<"Subtarget.isV9()">,
AssemblerPredicate<"FeatureV9">;
// HasNoV9 - This predicate is true when the target doesn't have V9
// instructions. Use of this is just a hack for the isel not having proper

23
llvm/test/MC/Sparc/sparcv9-instructions.s Normal file
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@ -0,0 +1,23 @@
! RUN: not llvm-mc %s -arch=sparc -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: error: invalid instruction mnemonic
! V8-NEXT: addc %g2, %g1, %g3
! V9: addx %g2, %g1, %g3 ! encoding: [0x86,0x40,0x80,0x01]
addc %g2, %g1, %g3
! V8: error: invalid instruction mnemonic
! V8-NEXT: addccc %g1, %g2, %g3
! V9: addxcc %g1, %g2, %g3 ! encoding: [0x86,0xc0,0x40,0x02]
addccc %g1, %g2, %g3
! V8: error: invalid instruction mnemonic
! V8-NEXT: subc %g2, %g1, %g3
! V9: subx %g2, %g1, %g3 ! encoding: [0x86,0x60,0x80,0x01]
subc %g2, %g1, %g3
! V8: error: invalid instruction mnemonic
! V8-NEXT: subccc %g1, %g2, %g3
! V9: subxcc %g1, %g2, %g3 ! encoding: [0x86,0xe0,0x40,0x02]
subccc %g1, %g2, %g3