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Akira, 

Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172579
This commit is contained in:
Jack Carter 2013-01-16 00:07:45 +00:00
parent 962c9089d9
commit e0c1e1a47e
7 changed files with 44 additions and 2 deletions
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5
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -1071,6 +1071,9 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
if (!isMips64())
return MatchOperand_NoMatch;
//if the first token is not '$' we have error
if (Parser.getTok().isNot(AsmToken::Dollar))
return MatchOperand_NoMatch;
@ -1088,7 +1091,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
Parser.getTok().getLoc());
op->setRegKind(MipsOperand::Kind_HWRegs);
op->setRegKind(MipsOperand::Kind_HW64Regs);
Operands.push_back(op);
Parser.Lex(); // Eat reg number

16
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -128,6 +128,11 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@ -454,6 +459,17 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
//Currently only hardware register 29 is supported
if (RegNo != 29)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
return MCDisassembler::Success;
}
static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,

2
llvm/lib/Target/Mips/MipsRegisterInfo.td
View File

@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
let ParserMatchClass = HWRegsAsmOperand;
}
def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
let ParserMatchClass = HW64RegsAsmOperand;
}

6
llvm/test/MC/Disassembler/Mips/mips32.txt
View File

@ -404,3 +404,9 @@
# CHECK: xori $9, $6, 17767
0x38 0xc9 0x45 0x67
# CHECK: .set push
# CHECK: .set mips32r2
# CHECK: rdhwr $5, $29
# CHECK: .set pop
0x7c 0x05 0xe8 0x3b

6
llvm/test/MC/Disassembler/Mips/mips32_le.txt
View File

@ -404,3 +404,9 @@
# CHECK: xori $9, $6, 17767
0x67 0x45 0xc9 0x38
# CHECK: .set push
# CHECK: .set mips32r2
# CHECK: rdhwr $5, $29
# CHECK: .set pop
0x3b 0xe8 0x05 0x7c

5
llvm/test/MC/Mips/mips-alu-instructions.s
View File

@ -81,6 +81,10 @@
# CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00]
# CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00]
# CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01]
# CHECK: .set push
# CHECK: .set mips32r2
# CHECK: rdhwr $5, $29
# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
add $9,$6,$7
add $9,$6,17767
addu $9,$6,-15001
@ -98,3 +102,4 @@
neg $6,$7
negu $6,$7
move $7,$8
rdhwr $5, $29

6
llvm/test/MC/Mips/mips64-alu-instructions.s
View File

@ -78,6 +78,11 @@
# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
# CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01]
# CHECK: .set push
# CHECK: .set mips32r2
# CHECK: rdhwr $5, $29
# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
dadd $9,$6,$7
dadd $9,$6,17767
daddu $9,$6,-15001
@ -92,3 +97,4 @@
multu $3,$5
dsubu $4,$3,$5
move $7,$8
rdhwr $5, $29