forked from OSchip/llvm-project
[PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang
This patch implements builtins for the following prototypes: unsigned long long __builtin_cfuged (unsigned long long, unsigned long long); vector unsigned long long vec_cfuge (vector unsigned long long, vector unsigned long long); unsigned long long vec_gnb (vector unsigned __int128, const unsigned int); vector unsigned char vec_ternarylogic (vector unsigned char, vector unsigned char, vector unsigned char, const unsigned int); vector unsigned short vec_ternarylogic (vector unsigned short, vector unsigned short, vector unsigned short, const unsigned int); vector unsigned int vec_ternarylogic (vector unsigned int, vector unsigned int, vector unsigned int, const unsigned int); vector unsigned long long vec_ternarylogic (vector unsigned long long, vector unsigned long long, vector unsigned long long, const unsigned int); vector unsigned __int128 vec_ternarylogic (vector unsigned __int128, vector unsigned __int128, vector unsigned __int128, const unsigned int); Differential Revision: https://reviews.llvm.org/D80970
This commit is contained in:
Amy Kwan
parent
0723b1891f
commit
e0c02dc980
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@ -302,6 +302,12 @@ BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
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BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
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BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
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// P10 Vector Centrifuge built-in.
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BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "")
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// P10 Vector Gather Every N-th Bit built-in.
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BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "")
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// P10 Vector Clear Bytes built-ins.
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BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
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BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
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@ -439,6 +445,8 @@ BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")
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BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
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BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
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BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
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// Float 128 built-ins
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BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "")
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BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "")
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@ -489,6 +497,7 @@ BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "")
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BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "")
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BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "")
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BUILTIN(__builtin_pextd, "ULLiULLiULLi", "")
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BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "")
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BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "")
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BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "")
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@ -16777,6 +16777,42 @@ vec_pext(vector unsigned long long __a, vector unsigned long long __b) {
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return __builtin_altivec_vpextd(__a, __b);
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}
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/* vec_cfuge */
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static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_cfuge(vector unsigned long long __a, vector unsigned long long __b) {
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return __builtin_altivec_vcfuged(__a, __b);
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}
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/* vec_gnb */
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#define vec_gnb(__a, __b) __builtin_altivec_vgnb(__a, __b)
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/* vec_ternarylogic */
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#ifdef __VSX__
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#define vec_ternarylogic(__a, __b, __c, __imm) \
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_Generic((__a), vector unsigned char \
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: __builtin_vsx_xxeval((vector unsigned long long)(__a), \
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(vector unsigned long long)(__b), \
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(vector unsigned long long)(__c), (__imm)), \
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vector unsigned short \
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: __builtin_vsx_xxeval((vector unsigned long long)(__a), \
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(vector unsigned long long)(__b), \
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(vector unsigned long long)(__c), (__imm)), \
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vector unsigned int \
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: __builtin_vsx_xxeval((vector unsigned long long)(__a), \
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(vector unsigned long long)(__b), \
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(vector unsigned long long)(__c), (__imm)), \
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vector unsigned long long \
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: __builtin_vsx_xxeval((vector unsigned long long)(__a), \
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(vector unsigned long long)(__b), \
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(vector unsigned long long)(__c), (__imm)), \
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vector unsigned __int128 \
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: __builtin_vsx_xxeval((vector unsigned long long)(__a), \
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(vector unsigned long long)(__b), \
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(vector unsigned long long)(__c), (__imm)))
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#endif /* __VSX__ */
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/* vec_genpcvm */
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#ifdef __VSX__
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@ -3124,6 +3124,10 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
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SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
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case PPC::BI__builtin_pack_vector_int128:
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return SemaVSXCheck(TheCall);
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case PPC::BI__builtin_altivec_vgnb:
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return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
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case PPC::BI__builtin_vsx_xxeval:
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return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255);
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}
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return SemaBuiltinConstantArgRange(TheCall, i, l, u);
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}
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@ -14,6 +14,11 @@ unsigned long long test_pextd(void) {
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return __builtin_pextd(ulla, ullb);
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}
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unsigned long long test_cfuged(void) {
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// CHECK: @llvm.ppc.cfuged
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return __builtin_cfuged(ulla, ullb);
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}
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unsigned long long test_cntlzdm(void) {
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// CHECK: @llvm.ppc.cntlzdm
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return __builtin_cntlzdm(ulla, ullb);
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@ -6,10 +6,11 @@
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#include <altivec.h>
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vector signed char vsca;
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vector unsigned char vuca;
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vector unsigned short vusa;
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vector unsigned int vuia;
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vector unsigned long long vulla, vullb;
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vector unsigned char vuca, vucb, vucc;
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vector unsigned short vusa, vusb, vusc;
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vector unsigned int vuia, vuib, vuic;
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vector unsigned long long vulla, vullb, vullc;
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vector unsigned __int128 vui128a, vui128b, vui128c;
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unsigned int uia;
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vector unsigned long long test_vpdepd(void) {
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@ -24,6 +25,60 @@ vector unsigned long long test_vpextd(void) {
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return vec_pext(vulla, vullb);
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}
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vector unsigned long long test_vcfuged(void) {
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// CHECK: @llvm.ppc.altivec.vcfuged(<2 x i64>
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// CHECK-NEXT: ret <2 x i64>
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return vec_cfuge(vulla, vullb);
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}
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unsigned long long test_vgnb_1(void) {
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// CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 2)
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// CHECK-NEXT: ret i64
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return vec_gnb(vui128a, 2);
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}
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unsigned long long test_vgnb_2(void) {
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// CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 7)
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// CHECK-NEXT: ret i64
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return vec_gnb(vui128a, 7);
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}
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unsigned long long test_vgnb_3(void) {
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// CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 5)
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// CHECK-NEXT: ret i64
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return vec_gnb(vui128a, 5);
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}
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vector unsigned char test_xxeval_uc(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 0)
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// CHECK: ret <16 x i8>
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return vec_ternarylogic(vuca, vucb, vucc, 0);
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}
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vector unsigned short test_xxeval_us(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 255)
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// CHECK: ret <8 x i16>
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return vec_ternarylogic(vusa, vusb, vusc, 255);
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}
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vector unsigned int test_xxeval_ui(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 150)
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// CHECK: ret <4 x i32>
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return vec_ternarylogic(vuia, vuib, vuic, 150);
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}
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vector unsigned long long test_xxeval_ull(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 1)
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// CHECK: ret <2 x i64>
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return vec_ternarylogic(vulla, vullb, vullc, 1);
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}
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vector unsigned __int128 test_xxeval_ui128(void) {
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// CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 246)
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// CHECK: ret <1 x i128>
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return vec_ternarylogic(vui128a, vui128b, vui128c, 246);
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}
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vector unsigned char test_xxgenpcvbm(void) {
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// CHECK: @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %{{.+}}, i32
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// CHECK-NEXT: ret <16 x i8>
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@ -68,6 +68,11 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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: GCCBuiltin<"__builtin_pextd">,
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Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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// Centrifuge Doubleword Builtin.
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def int_ppc_cfuged
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: GCCBuiltin<"__builtin_cfuged">,
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Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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// Count Leading / Trailing Zeroes under bit Mask Builtins.
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def int_ppc_cntlzdm
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: GCCBuiltin<"__builtin_cntlzdm">,
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@ -426,6 +431,16 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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// P10 Vector Centrifuge Builtin.
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def int_ppc_altivec_vcfuged : GCCBuiltin<"__builtin_altivec_vcfuged">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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// P10 Vector Gather Every Nth Bit Builtin.
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def int_ppc_altivec_vgnb : GCCBuiltin<"__builtin_altivec_vgnb">,
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Intrinsic<[llvm_i64_ty], [llvm_v1i128_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<1>>]>;
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// P10 Vector Clear Bytes
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def int_ppc_altivec_vclrlb : GCCBuiltin<"__builtin_altivec_vclrlb">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
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@ -969,6 +984,11 @@ def int_ppc_vsx_xxinsertw :
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PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
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[llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
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[IntrNoMem]>;
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def int_ppc_vsx_xxeval :
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PowerPC_VSX_Intrinsic<"xxeval", [llvm_v2i64_ty],
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[llvm_v2i64_ty, llvm_v2i64_ty,
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llvm_v2i64_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<3>>]>;
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def int_ppc_vsx_xxgenpcvbm :
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PowerPC_VSX_Intrinsic<"xxgenpcvbm", [llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
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@ -177,6 +177,54 @@ class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
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let Inst{31} = XT{5};
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}
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class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo,
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dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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bits<6> XC;
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bits<8> IMM;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 1;
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let Inst{8} = 0;
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let Inst{9-11} = 0;
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let Inst{12-13} = 0;
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let Inst{14-23} = 0;
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let Inst{24-31} = IMM;
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// The instruction.
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let Inst{38-42} = XT{4-0};
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let Inst{43-47} = XA{4-0};
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let Inst{48-52} = XB{4-0};
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let Inst{53-57} = XC{4-0};
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let Inst{58-59} = xo;
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let Inst{60} = XC{5};
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let Inst{61} = XA{5};
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let Inst{62} = XB{5};
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let Inst{63} = XT{5};
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}
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class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OOL, IOL, asmstr, itin> {
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bits<5> RD;
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bits<5> VB;
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bits<3> N;
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let Pattern = pattern;
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let Inst{6-10} = RD;
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let Inst{11-12} = 0;
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let Inst{13-15} = N;
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let Inst{16-20} = VB;
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let Inst{21-31} = xo;
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}
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multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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@ -532,6 +580,23 @@ let Predicates = [IsISA3_1] in {
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def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"pextd $rA, $rS, $rB", IIC_IntGeneral,
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[(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
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def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vcfuged $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD,
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(int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>;
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def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N),
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"vgnb $rD, $vB, $N", IIC_VecGeneral,
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[(set i64:$rD,
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(int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>;
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def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"cfuged $rA, $rS, $rB", IIC_IntGeneral,
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[(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>;
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def XXEVAL :
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8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
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vsrc:$XC, u8imm:$IMM),
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"xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
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[(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
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v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
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def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vclzdm $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD,
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@ -9,6 +9,10 @@ declare <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.pdepd(i64, i64)
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declare i64 @llvm.ppc.pextd(i64, i64)
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declare <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.cfuged(i64, i64)
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declare i64 @llvm.ppc.altivec.vgnb(<1 x i128>, i32)
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declare <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64>, <2 x i64>, <2 x i64>, i32)
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declare <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.cntlzdm(i64, i64)
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@ -54,6 +58,66 @@ entry:
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ret i64 %tmp
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}
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define <2 x i64> @test_vcfuged(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vcfuged:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vcfuged v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define i64 @test_cfuged(i64 %a, i64 %b) {
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; CHECK-LABEL: test_cfuged:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cfuged r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.cfuged(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @test_vgnb_1(<1 x i128> %a) {
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; CHECK-LABEL: test_vgnb_1:
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; CHECK: # %bb.0: # %entry
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||||
; CHECK-NEXT: vgnb r3, v2, 2
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 2)
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i64 @test_vgnb_2(<1 x i128> %a) {
|
||||
; CHECK-LABEL: test_vgnb_2:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vgnb r3, v2, 7
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 7)
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define i64 @test_vgnb_3(<1 x i128> %a) {
|
||||
; CHECK-LABEL: test_vgnb_3:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vgnb r3, v2, 5
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 5)
|
||||
ret i64 %tmp
|
||||
}
|
||||
|
||||
define <2 x i64> @test_xxeval(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
|
||||
; CHECK-LABEL: test_xxeval:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xxeval v2, v2, v3, v4, 255
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%tmp = tail call <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, i32 255)
|
||||
ret <2 x i64> %tmp
|
||||
}
|
||||
|
||||
define <2 x i64> @test_vclzdm(<2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-LABEL: test_vclzdm:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
|
|
|
|||
|
|
@ -13,6 +13,18 @@
|
|||
# CHECK: pextd 1, 2, 4
|
||||
0x7c 0x41 0x21 0x78
|
||||
|
||||
# CHECK: vcfuged 1, 2, 4
|
||||
0x10 0x22 0x25 0x4d
|
||||
|
||||
# CHECK: cfuged 1, 2, 4
|
||||
0x7c 0x41 0x21 0xb8
|
||||
|
||||
# CHECK: vgnb 1, 2, 2
|
||||
0x10 0x22 0x14 0xcc
|
||||
|
||||
# CHECK: xxeval 32, 1, 2, 3, 2
|
||||
0x05 0x00 0x00 0x02 0x88 0x01 0x10 0xd1
|
||||
|
||||
# CHECK: vclzdm 1, 2, 3
|
||||
0x10 0x22 0x1f 0x84
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,20 @@
|
|||
# CHECK-BE: pextd 1, 2, 4 # encoding: [0x7c,0x41,0x21,0x78]
|
||||
# CHECK-LE: pextd 1, 2, 4 # encoding: [0x78,0x21,0x41,0x7c]
|
||||
pextd 1, 2, 4
|
||||
# CHECK-BE: vcfuged 1, 2, 4 # encoding: [0x10,0x22,0x25,0x4d]
|
||||
# CHECK-LE: vcfuged 1, 2, 4 # encoding: [0x4d,0x25,0x22,0x10]
|
||||
vcfuged 1, 2, 4
|
||||
# CHECK-BE: cfuged 1, 2, 4 # encoding: [0x7c,0x41,0x21,0xb8]
|
||||
# CHECK-LE: cfuged 1, 2, 4 # encoding: [0xb8,0x21,0x41,0x7c]
|
||||
cfuged 1, 2, 4
|
||||
# CHECK-BE: vgnb 1, 2, 2 # encoding: [0x10,0x22,0x14,0xcc]
|
||||
# CHECK-LE: vgnb 1, 2, 2 # encoding: [0xcc,0x14,0x22,0x10]
|
||||
vgnb 1, 2, 2
|
||||
# CHECK-BE: xxeval 32, 1, 2, 3, 2 # encoding: [0x05,0x00,0x00,0x02,
|
||||
# CHECK-BE-SAME: 0x88,0x01,0x10,0xd1]
|
||||
# CHECK-LE: xxeval 32, 1, 2, 3, 2 # encoding: [0x02,0x00,0x00,0x05,
|
||||
# CHECK-LE-SAME: 0xd1,0x10,0x01,0x88]
|
||||
xxeval 32, 1, 2, 3, 2
|
||||
# CHECK-BE: vclzdm 1, 2, 3 # encoding: [0x10,0x22,0x1f,0x84]
|
||||
# CHECK-LE: vclzdm 1, 2, 3 # encoding: [0x84,0x1f,0x22,0x10]
|
||||
vclzdm 1, 2, 3
|
||||
|
|
|
|||
Loading…
Reference in New Issue