forked from OSchip/llvm-project
AMDGPU: Don't use stack space for SGPR->VGPR spills
Before frame offsets are calculated, try to eliminate the frame indexes used by SGPR spills. Then we can delete them after. I think for now we can be sure that no other instruction will be re-using the same frame indexes. It should be easy to notice if this assumption ever breaks since everything asserts if it tries to use a dead frame index later. The unused emergency stack slot seems to still be left behind, so an additional 4 bytes is still wasted. llvm-svn: 295753
This commit is contained in:
Matt Arsenault
parent
ebfe01c121
commit
e0bf7d02f0
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@ -128,13 +128,12 @@ unsigned SIFrameLowering::getReservedPrivateSegmentBufferReg(
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ArrayRef<MCPhysReg> AllSGPR128s = getAllSGPR128(ST, MF);
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AllSGPR128s = AllSGPR128s.slice(std::min(static_cast<unsigned>(AllSGPR128s.size()), NumPreloaded));
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// Skip the last 2 elements because the last one is reserved for VCC, and
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// this is the 2nd to last element already.
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// Skip the last N reserved elements because they should have already been
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// reserved for VCC etc.
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for (MCPhysReg Reg : AllSGPR128s) {
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// Pick the first unallocated one. Make sure we don't clobber the other
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// reserved input we needed.
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if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) {
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//assert(MRI.isAllocatable(Reg));
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MRI.replaceRegWith(ScratchRsrcReg, Reg);
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MFI->setScratchRSrcReg(Reg);
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return Reg;
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@ -157,7 +156,6 @@ unsigned SIFrameLowering::getReservedPrivateSegmentWaveByteOffsetReg(
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unsigned ScratchRsrcReg = MFI->getScratchRSrcReg();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned NumPreloaded = MFI->getNumPreloadedSGPRs();
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ArrayRef<MCPhysReg> AllSGPRs = getAllSGPRs(ST, MF);
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@ -393,17 +391,45 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
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if (!MFI.hasStackObjects())
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return;
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bool MayNeedScavengingEmergencySlot = MFI.hasStackObjects();
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assert(RS && "RegScavenger required if spilling");
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int ScavengeFI = MFI.CreateStackObject(
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AMDGPU::SGPR_32RegClass.getSize(),
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AMDGPU::SGPR_32RegClass.getAlignment(), false);
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RS->addScavengingFrameIndex(ScavengeFI);
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assert((RS || !MayNeedScavengingEmergencySlot) &&
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"RegScavenger required if spilling");
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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if (!TRI.spillSGPRToVGPR())
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return;
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if (MayNeedScavengingEmergencySlot) {
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int ScavengeFI = MFI.CreateStackObject(
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AMDGPU::SGPR_32RegClass.getSize(),
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AMDGPU::SGPR_32RegClass.getAlignment(), false);
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RS->addScavengingFrameIndex(ScavengeFI);
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SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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if (!FuncInfo->hasSpilledSGPRs())
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return;
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// Process all SGPR spills before frame offsets are finalized. Ideally SGPRs
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// are spilled to VGPRs, in which case we can eliminate the stack usage.
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//
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// XXX - This operates under the assumption that only other SGPR spills are
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// users of the frame index. I'm not 100% sure this is correct. The
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// StackColoring pass has a comment saying a future improvement would be to
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// merging of allocas with spill slots, but for now according to
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// MachineFrameInfo isSpillSlot can't alias any other object.
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for (MachineBasicBlock &MBB : MF) {
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MachineBasicBlock::iterator Next;
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for (auto I = MBB.begin(), E = MBB.end(); I != E; I = Next) {
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MachineInstr &MI = *I;
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Next = std::next(I);
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if (TII->isSGPRSpill(MI)) {
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int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
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if (FuncInfo->allocateSGPRSpillToVGPR(MF, FI))
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TRI.eliminateSGPRToVGPRSpillFrameIndex(MI, FI, RS);
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}
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}
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}
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FuncInfo->removeSGPRToVGPRFrameIndices(MFI);
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}
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void SIFrameLowering::emitDebuggerPrologue(MachineFunction &MF,
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@ -4673,6 +4673,8 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
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case 256:
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return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
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case 512:
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return std::make_pair(0U, &AMDGPU::SReg_512RegClass);
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}
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case 'v':
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@ -36,7 +36,7 @@ BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
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cl::desc("Restrict range of branch instructions (DEBUG)"));
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SIInstrInfo::SIInstrInfo(const SISubtarget &ST)
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: AMDGPUInstrInfo(ST), RI(), ST(ST) {}
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: AMDGPUInstrInfo(ST), RI(ST), ST(ST) {}
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//===----------------------------------------------------------------------===//
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// TargetInstrInfo callbacks
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@ -20,12 +20,6 @@
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using namespace llvm;
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static cl::opt<bool> EnableSpillSGPRToVGPR(
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"amdgpu-spill-sgpr-to-vgpr",
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cl::desc("Enable spilling VGPRs to SGPRs"),
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cl::ReallyHidden,
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cl::init(true));
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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TIDReg(AMDGPU::NoRegister),
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@ -193,45 +187,60 @@ unsigned SIMachineFunctionInfo::addPrivateMemoryPtr(const SIRegisterInfo &TRI) {
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return PrivateMemoryPtrUserSGPR;
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}
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SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg (
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MachineFunction *MF,
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unsigned FrameIndex,
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unsigned SubIdx) {
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if (!EnableSpillSGPRToVGPR)
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return SpilledReg();
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/// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
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bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
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int FI) {
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std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
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const SISubtarget &ST = MF->getSubtarget<SISubtarget>();
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// This has already been allocated.
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if (!SpillLanes.empty())
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return true;
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned WaveSize = ST.getWavefrontSize();
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MachineFrameInfo &FrameInfo = MF->getFrameInfo();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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int64_t Offset = FrameInfo.getObjectOffset(FrameIndex);
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Offset += SubIdx * 4;
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unsigned Size = FrameInfo.getObjectSize(FI);
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assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
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assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
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unsigned LaneVGPRIdx = Offset / (64 * 4);
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unsigned Lane = (Offset / 4) % 64;
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int NumLanes = Size / 4;
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struct SpilledReg Spill;
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Spill.Lane = Lane;
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// Make sure to handle the case where a wide SGPR spill may span between two
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// VGPRs.
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for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
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unsigned LaneVGPR;
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unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
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if (!LaneVGPRs.count(LaneVGPRIdx)) {
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unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
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*MF);
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if (VGPRIndex == 0) {
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LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
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if (LaneVGPR == AMDGPU::NoRegister) {
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// We have no VGPRs left for spilling SGPRs. Reset because we won't
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// partially spill the SGPR to VGPRs.
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SGPRToVGPRSpills.erase(FI);
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NumVGPRSpillLanes -= I;
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return false;
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}
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if (LaneVGPR == AMDGPU::NoRegister)
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// We have no VGPRs left for spilling SGPRs.
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return Spill;
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SpillVGPRs.push_back(LaneVGPR);
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LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
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BI != BE; ++BI) {
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BI->addLiveIn(LaneVGPR);
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineBasicBlock &BB : MF)
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BB.addLiveIn(LaneVGPR);
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} else {
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LaneVGPR = SpillVGPRs.back();
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}
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SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
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}
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Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
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return Spill;
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return true;
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}
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void SIMachineFunctionInfo::removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI) {
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for (auto &R : SGPRToVGPRSpills)
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MFI.RemoveStackObject(R.first);
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}
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@ -134,7 +134,8 @@ public:
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// FIXME: Make private
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unsigned LDSWaveSpillSize;
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unsigned PSInputEna;
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std::map<unsigned, unsigned> LaneVGPRs;
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unsigned ScratchOffsetReg;
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unsigned NumUserSGPRs;
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unsigned NumSystemSGPRs;
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@ -195,12 +196,29 @@ public:
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bool hasReg() { return VGPR != AMDGPU::NoRegister;}
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};
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// SIMachineFunctionInfo definition
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private:
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// SGPR->VGPR spilling support.
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typedef std::pair<unsigned, unsigned> SpillRegMask;
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// Track VGPR + wave index for each subregister of the SGPR spilled to
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// frameindex key.
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DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
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unsigned NumVGPRSpillLanes = 0;
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SmallVector<unsigned, 2> SpillVGPRs;
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public:
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SIMachineFunctionInfo(const MachineFunction &MF);
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SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
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unsigned SubIdx);
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ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
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auto I = SGPRToVGPRSpills.find(FrameIndex);
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return (I == SGPRToVGPRSpills.end()) ?
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ArrayRef<SpilledReg>() : makeArrayRef(I->second);
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}
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bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
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void removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI);
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bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
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unsigned getTIDReg() const { return TIDReg; };
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void setTIDReg(unsigned Reg) { TIDReg = Reg; }
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@ -24,12 +24,6 @@
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using namespace llvm;
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static cl::opt<bool> EnableSpillSGPRToSMEM(
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"amdgpu-spill-sgpr-to-smem",
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cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"),
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cl::init(false));
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static bool hasPressureSet(const int *PSets, unsigned PSetID) {
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for (unsigned i = 0; PSets[i] != -1; ++i) {
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if (PSets[i] == (int)PSetID)
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@ -49,9 +43,28 @@ void SIRegisterInfo::classifyPressureSet(unsigned PSetID, unsigned Reg,
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}
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}
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SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo(),
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SGPRPressureSets(getNumRegPressureSets()),
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VGPRPressureSets(getNumRegPressureSets()) {
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static cl::opt<bool> EnableSpillSGPRToSMEM(
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"amdgpu-spill-sgpr-to-smem",
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cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"),
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cl::init(false));
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static cl::opt<bool> EnableSpillSGPRToVGPR(
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"amdgpu-spill-sgpr-to-vgpr",
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cl::desc("Enable spilling VGPRs to SGPRs"),
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cl::ReallyHidden,
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cl::init(true));
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SIRegisterInfo::SIRegisterInfo(const SISubtarget &ST) :
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AMDGPURegisterInfo(),
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SGPRPressureSets(getNumRegPressureSets()),
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VGPRPressureSets(getNumRegPressureSets()),
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SpillSGPRToVGPR(false),
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SpillSGPRToSMEM(false) {
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if (EnableSpillSGPRToSMEM && ST.hasScalarStores())
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SpillSGPRToSMEM = true;
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else if (EnableSpillSGPRToVGPR)
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SpillSGPRToVGPR = true;
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unsigned NumRegPressureSets = getNumRegPressureSets();
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SGPRSetID = NumRegPressureSets;
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@ -557,11 +570,20 @@ static std::pair<unsigned, unsigned> getSpillEltSize(unsigned SuperRegSize,
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AMDGPU::S_BUFFER_LOAD_DWORD_SGPR};
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}
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void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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int Index,
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RegScavenger *RS) const {
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RegScavenger *RS,
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bool OnlyToVGPR) const {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction *MF = MBB->getParent();
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SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
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ArrayRef<SIMachineFunctionInfo::SpilledReg> VGPRSpills
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= MFI->getSGPRToVGPRSpills(Index);
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bool SpillToVGPR = !VGPRSpills.empty();
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if (OnlyToVGPR && !SpillToVGPR)
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return false;
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const SISubtarget &ST = MF->getSubtarget<SISubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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@ -570,10 +592,11 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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bool IsKill = MI->getOperand(0).isKill();
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const DebugLoc &DL = MI->getDebugLoc();
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SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
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MachineFrameInfo &FrameInfo = MF->getFrameInfo();
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bool SpillToSMEM = ST.hasScalarStores() && EnableSpillSGPRToSMEM;
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bool SpillToSMEM = spillSGPRToSMEM();
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if (SpillToSMEM && OnlyToVGPR)
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return false;
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assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
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@ -646,9 +669,9 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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continue;
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}
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struct SIMachineFunctionInfo::SpilledReg Spill =
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MFI->getSpilledReg(MF, Index, i);
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if (Spill.hasReg()) {
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if (SpillToVGPR) {
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SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
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BuildMI(*MBB, MI, DL,
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TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
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Spill.VGPR)
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@ -659,6 +682,10 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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// frame index, we should delete the frame index when all references to
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// it are fixed.
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} else {
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// XXX - Can to VGPR spill fail for some subregisters but not others?
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if (OnlyToVGPR)
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return false;
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// Spill SGPR to a frame index.
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// TODO: Should VI try to spill to VGPR and then spill to SMEM?
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unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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@ -702,22 +729,33 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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MI->eraseFromParent();
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MFI->addToSpilledSGPRs(NumSubRegs);
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return true;
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}
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void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
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bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
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int Index,
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RegScavenger *RS) const {
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RegScavenger *RS,
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bool OnlyToVGPR) const {
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MachineFunction *MF = MI->getParent()->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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MachineBasicBlock *MBB = MI->getParent();
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SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
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ArrayRef<SIMachineFunctionInfo::SpilledReg> VGPRSpills
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= MFI->getSGPRToVGPRSpills(Index);
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bool SpillToVGPR = !VGPRSpills.empty();
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if (OnlyToVGPR && !SpillToVGPR)
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return false;
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MachineFrameInfo &FrameInfo = MF->getFrameInfo();
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const SISubtarget &ST = MF->getSubtarget<SISubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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const DebugLoc &DL = MI->getDebugLoc();
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unsigned SuperReg = MI->getOperand(0).getReg();
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bool SpillToSMEM = ST.hasScalarStores() && EnableSpillSGPRToSMEM;
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bool SpillToSMEM = spillSGPRToSMEM();
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if (SpillToSMEM && OnlyToVGPR)
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return false;
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assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
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@ -785,10 +823,8 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
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continue;
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}
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SIMachineFunctionInfo::SpilledReg Spill
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= MFI->getSpilledReg(MF, Index, i);
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if (Spill.hasReg()) {
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if (SpillToVGPR) {
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SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
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auto MIB =
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BuildMI(*MBB, MI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
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SubReg)
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@ -798,6 +834,9 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
|
|||
if (NumSubRegs > 1)
|
||||
MIB.addReg(SuperReg, RegState::ImplicitDefine);
|
||||
} else {
|
||||
if (OnlyToVGPR)
|
||||
return false;
|
||||
|
||||
// Restore SGPR from a stack slot.
|
||||
// FIXME: We should use S_LOAD_DWORD here for VI.
|
||||
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
|
||||
|
|
@ -832,6 +871,32 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
|
|||
}
|
||||
|
||||
MI->eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
/// Special case of eliminateFrameIndex. Returns true if the SGPR was spilled to
|
||||
/// a VGPR and the stack slot can be safely eliminated when all other users are
|
||||
/// handled.
|
||||
bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex(
|
||||
MachineBasicBlock::iterator MI,
|
||||
int FI,
|
||||
RegScavenger *RS) const {
|
||||
switch (MI->getOpcode()) {
|
||||
case AMDGPU::SI_SPILL_S512_SAVE:
|
||||
case AMDGPU::SI_SPILL_S256_SAVE:
|
||||
case AMDGPU::SI_SPILL_S128_SAVE:
|
||||
case AMDGPU::SI_SPILL_S64_SAVE:
|
||||
case AMDGPU::SI_SPILL_S32_SAVE:
|
||||
return spillSGPR(MI, FI, RS, true);
|
||||
case AMDGPU::SI_SPILL_S512_RESTORE:
|
||||
case AMDGPU::SI_SPILL_S256_RESTORE:
|
||||
case AMDGPU::SI_SPILL_S128_RESTORE:
|
||||
case AMDGPU::SI_SPILL_S64_RESTORE:
|
||||
case AMDGPU::SI_SPILL_S32_RESTORE:
|
||||
return restoreSGPR(MI, FI, RS, true);
|
||||
default:
|
||||
llvm_unreachable("not an SGPR spill instruction");
|
||||
}
|
||||
}
|
||||
|
||||
void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
|
|
|
|||
|
|
@ -21,8 +21,8 @@
|
|||
|
||||
namespace llvm {
|
||||
|
||||
class SISubtarget;
|
||||
class MachineRegisterInfo;
|
||||
class SISubtarget;
|
||||
class SIMachineFunctionInfo;
|
||||
|
||||
class SIRegisterInfo final : public AMDGPURegisterInfo {
|
||||
|
|
@ -31,13 +31,22 @@ private:
|
|||
unsigned VGPRSetID;
|
||||
BitVector SGPRPressureSets;
|
||||
BitVector VGPRPressureSets;
|
||||
bool SpillSGPRToVGPR;
|
||||
bool SpillSGPRToSMEM;
|
||||
|
||||
void reserveRegisterTuples(BitVector &, unsigned Reg) const;
|
||||
void classifyPressureSet(unsigned PSetID, unsigned Reg,
|
||||
BitVector &PressureSets) const;
|
||||
|
||||
public:
|
||||
SIRegisterInfo();
|
||||
SIRegisterInfo(const SISubtarget &ST);
|
||||
|
||||
bool spillSGPRToVGPR() const {
|
||||
return SpillSGPRToVGPR;
|
||||
}
|
||||
|
||||
bool spillSGPRToSMEM() const {
|
||||
return SpillSGPRToSMEM;
|
||||
}
|
||||
|
||||
/// Return the end register initially reserved for the scratch buffer in case
|
||||
/// spilling is needed.
|
||||
|
|
@ -78,16 +87,22 @@ public:
|
|||
const TargetRegisterClass *getPointerRegClass(
|
||||
const MachineFunction &MF, unsigned Kind = 0) const override;
|
||||
|
||||
void spillSGPR(MachineBasicBlock::iterator MI,
|
||||
int FI, RegScavenger *RS) const;
|
||||
/// If \p OnlyToVGPR is true, this will only succeed if this
|
||||
bool spillSGPR(MachineBasicBlock::iterator MI,
|
||||
int FI, RegScavenger *RS,
|
||||
bool OnlyToVGPR = false) const;
|
||||
|
||||
void restoreSGPR(MachineBasicBlock::iterator MI,
|
||||
int FI, RegScavenger *RS) const;
|
||||
bool restoreSGPR(MachineBasicBlock::iterator MI,
|
||||
int FI, RegScavenger *RS,
|
||||
bool OnlyToVGPR = false) const;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS) const override;
|
||||
|
||||
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI,
|
||||
int FI, RegScavenger *RS) const;
|
||||
|
||||
unsigned getHWRegIndex(unsigned Reg) const {
|
||||
return getEncodingValue(Reg) & 0xff;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -325,7 +325,7 @@ def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {
|
|||
let AllocationPriority = 11;
|
||||
}
|
||||
|
||||
def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> {
|
||||
def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add SGPR_512)> {
|
||||
// Requires 8 s_mov_b64 to copy
|
||||
let CopyCost = 8;
|
||||
let AllocationPriority = 12;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
|
||||
|
||||
; GCN-LABEL: {{^}}divergent_if_endif:
|
||||
; VGPR: workitem_private_segment_byte_size = 12{{$}}
|
||||
|
||||
|
||||
; GCN: {{^}}; BB#0:
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
|
|
@ -31,7 +33,9 @@
|
|||
; VMEM: buffer_store_dword v[[V_SAVEEXEC_HI]], off, s[0:3], s7 offset:4 ; 4-byte Folded Spill
|
||||
|
||||
; Spill load
|
||||
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s7 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
|
||||
; VMEM: buffer_store_dword [[LOAD0]], off, s[0:3], s7 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
|
||||
; VGPR: buffer_store_dword [[LOAD0]], off, s[0:3], s7 ; 4-byte Folded Spill
|
||||
|
||||
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
|
||||
|
||||
; GCN: s_waitcnt vmcnt(0) expcnt(0)
|
||||
|
|
@ -40,7 +44,8 @@
|
|||
; GCN: {{^}}BB{{[0-9]+}}_1: ; %if
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]
|
||||
; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
|
||||
; VMEM: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
|
||||
; VGPR: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 ; 4-byte Folded Reload
|
||||
; GCN: s_waitcnt vmcnt(0)
|
||||
|
||||
; Spill val register
|
||||
|
|
@ -88,6 +93,8 @@ endif:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}divergent_loop:
|
||||
; VGPR: workitem_private_segment_byte_size = 16{{$}}
|
||||
|
||||
; GCN: {{^}}; BB#0:
|
||||
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,635 @@
|
|||
; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s
|
||||
|
||||
; Spill all SGPRs so multiple VGPRs are required for spilling all of them.
|
||||
|
||||
; Ideally we only need 2 VGPRs for all spilling. The VGPRs are
|
||||
; allocated per-frame index, so it's possible to get up with more.
|
||||
|
||||
; GCN-LABEL: {{^}}spill_sgprs_to_multiple_vgprs:
|
||||
|
||||
; GCN: def s[8:15]
|
||||
; GCN: def s[16:23]
|
||||
; GCN: def s[24:31]
|
||||
; GCN: def s[32:39]
|
||||
; GCN: def s[40:47]
|
||||
; GCN: def s[48:55]
|
||||
; GCN: def s[56:63]
|
||||
; GCN: def s[64:71]
|
||||
; GCN: def s[72:79]
|
||||
; GCN: def s[80:87]
|
||||
; GCN: def s[88:95]
|
||||
|
||||
; GCN: v_writelane_b32 v0, s8, 0
|
||||
; GCN-NEXT: v_writelane_b32 v0, s9, 1
|
||||
; GCN-NEXT: v_writelane_b32 v0, s10, 2
|
||||
; GCN-NEXT: v_writelane_b32 v0, s11, 3
|
||||
; GCN-NEXT: v_writelane_b32 v0, s12, 4
|
||||
; GCN-NEXT: v_writelane_b32 v0, s13, 5
|
||||
; GCN-NEXT: v_writelane_b32 v0, s14, 6
|
||||
; GCN-NEXT: v_writelane_b32 v0, s15, 7
|
||||
|
||||
; GCN: def s{{\[}}[[TMP_LO:[0-9]+]]:[[TMP_HI:[0-9]+]]{{\]}}
|
||||
; GCN: v_writelane_b32 v0, s[[TMP_LO]], 8
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 9
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 10
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 11
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 12
|
||||
; GCN-NEXT: v_writelane_b32 v0, s13, 13
|
||||
; GCN-NEXT: v_writelane_b32 v0, s14, 14
|
||||
; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 15
|
||||
|
||||
; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}}
|
||||
; GCN: v_writelane_b32 v0, s[[TMP_LO]], 16
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 17
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 18
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 19
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 20
|
||||
; GCN-NEXT: v_writelane_b32 v0, s13, 21
|
||||
; GCN-NEXT: v_writelane_b32 v0, s14, 22
|
||||
; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 23
|
||||
|
||||
; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}}
|
||||
; GCN: v_writelane_b32 v0, s[[TMP_LO]], 24
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 25
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 26
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 27
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 28
|
||||
; GCN-NEXT: v_writelane_b32 v0, s13, 29
|
||||
; GCN-NEXT: v_writelane_b32 v0, s14, 30
|
||||
; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 31
|
||||
|
||||
; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}}
|
||||
; GCN: v_writelane_b32 v0, s[[TMP_LO]], 32
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 33
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 34
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 35
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 36
|
||||
; GCN-NEXT: v_writelane_b32 v0, s13, 37
|
||||
; GCN-NEXT: v_writelane_b32 v0, s14, 38
|
||||
; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 39
|
||||
|
||||
; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}}
|
||||
; GCN: v_writelane_b32 v0, s[[TMP_LO]], 40
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 41
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 42
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 43
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 44
|
||||
; GCN-NEXT: v_writelane_b32 v0, s13, 45
|
||||
; GCN-NEXT: v_writelane_b32 v0, s14, 46
|
||||
; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 47
|
||||
|
||||
; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}}
|
||||
; GCN: v_writelane_b32 v0, s[[TMP_LO]], 48
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 49
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 50
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 51
|
||||
; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 52
|
||||
; GCN-NEXT: v_writelane_b32 v0, s13, 53
|
||||
; GCN-NEXT: v_writelane_b32 v0, s14, 54
|
||||
; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 55
|
||||
|
||||
; GCN-NEXT: v_writelane_b32 v0, s88, 56
|
||||
; GCN-NEXT: v_writelane_b32 v0, s89, 57
|
||||
; GCN-NEXT: v_writelane_b32 v0, s90, 58
|
||||
; GCN-NEXT: v_writelane_b32 v0, s91, 59
|
||||
; GCN-NEXT: v_writelane_b32 v0, s92, 60
|
||||
; GCN-NEXT: v_writelane_b32 v0, s93, 61
|
||||
; GCN-NEXT: v_writelane_b32 v0, s94, 62
|
||||
; GCN-NEXT: v_writelane_b32 v0, s95, 63
|
||||
; GCN-NEXT: v_writelane_b32 v1, s16, 0
|
||||
; GCN-NEXT: v_writelane_b32 v1, s17, 1
|
||||
; GCN-NEXT: v_writelane_b32 v1, s18, 2
|
||||
; GCN-NEXT: v_writelane_b32 v1, s19, 3
|
||||
; GCN-NEXT: v_writelane_b32 v1, s20, 4
|
||||
; GCN-NEXT: v_writelane_b32 v1, s21, 5
|
||||
; GCN-NEXT: v_writelane_b32 v1, s22, 6
|
||||
; GCN-NEXT: v_writelane_b32 v1, s23, 7
|
||||
; GCN-NEXT: v_writelane_b32 v1, s24, 8
|
||||
; GCN-NEXT: v_writelane_b32 v1, s25, 9
|
||||
; GCN-NEXT: v_writelane_b32 v1, s26, 10
|
||||
; GCN-NEXT: v_writelane_b32 v1, s27, 11
|
||||
; GCN-NEXT: v_writelane_b32 v1, s28, 12
|
||||
; GCN-NEXT: v_writelane_b32 v1, s29, 13
|
||||
; GCN-NEXT: v_writelane_b32 v1, s30, 14
|
||||
; GCN-NEXT: v_writelane_b32 v1, s31, 15
|
||||
; GCN-NEXT: v_writelane_b32 v1, s32, 16
|
||||
; GCN-NEXT: v_writelane_b32 v1, s33, 17
|
||||
; GCN-NEXT: v_writelane_b32 v1, s34, 18
|
||||
; GCN-NEXT: v_writelane_b32 v1, s35, 19
|
||||
; GCN-NEXT: v_writelane_b32 v1, s36, 20
|
||||
; GCN-NEXT: v_writelane_b32 v1, s37, 21
|
||||
; GCN-NEXT: v_writelane_b32 v1, s38, 22
|
||||
; GCN-NEXT: v_writelane_b32 v1, s39, 23
|
||||
; GCN-NEXT: v_writelane_b32 v1, s40, 24
|
||||
; GCN-NEXT: v_writelane_b32 v1, s41, 25
|
||||
; GCN-NEXT: v_writelane_b32 v1, s42, 26
|
||||
; GCN-NEXT: v_writelane_b32 v1, s43, 27
|
||||
; GCN-NEXT: v_writelane_b32 v1, s44, 28
|
||||
; GCN-NEXT: v_writelane_b32 v1, s45, 29
|
||||
; GCN-NEXT: v_writelane_b32 v1, s46, 30
|
||||
; GCN-NEXT: v_writelane_b32 v1, s47, 31
|
||||
; GCN-NEXT: v_writelane_b32 v1, s48, 32
|
||||
; GCN-NEXT: v_writelane_b32 v1, s49, 33
|
||||
; GCN-NEXT: v_writelane_b32 v1, s50, 34
|
||||
; GCN-NEXT: v_writelane_b32 v1, s51, 35
|
||||
; GCN-NEXT: v_writelane_b32 v1, s52, 36
|
||||
; GCN-NEXT: v_writelane_b32 v1, s53, 37
|
||||
; GCN-NEXT: v_writelane_b32 v1, s54, 38
|
||||
; GCN-NEXT: v_writelane_b32 v1, s55, 39
|
||||
; GCN-NEXT: v_writelane_b32 v1, s56, 40
|
||||
; GCN-NEXT: v_writelane_b32 v1, s57, 41
|
||||
; GCN-NEXT: v_writelane_b32 v1, s58, 42
|
||||
; GCN-NEXT: v_writelane_b32 v1, s59, 43
|
||||
; GCN-NEXT: v_writelane_b32 v1, s60, 44
|
||||
; GCN-NEXT: v_writelane_b32 v1, s61, 45
|
||||
; GCN-NEXT: v_writelane_b32 v1, s62, 46
|
||||
; GCN-NEXT: v_writelane_b32 v1, s63, 47
|
||||
; GCN-NEXT: v_writelane_b32 v1, s64, 48
|
||||
; GCN-NEXT: v_writelane_b32 v1, s65, 49
|
||||
; GCN-NEXT: v_writelane_b32 v1, s66, 50
|
||||
; GCN-NEXT: v_writelane_b32 v1, s67, 51
|
||||
; GCN-NEXT: v_writelane_b32 v1, s68, 52
|
||||
; GCN-NEXT: v_writelane_b32 v1, s69, 53
|
||||
; GCN-NEXT: v_writelane_b32 v1, s70, 54
|
||||
; GCN-NEXT: v_writelane_b32 v1, s71, 55
|
||||
; GCN-NEXT: v_writelane_b32 v1, s72, 56
|
||||
; GCN-NEXT: v_writelane_b32 v1, s73, 57
|
||||
; GCN-NEXT: v_writelane_b32 v1, s74, 58
|
||||
; GCN-NEXT: v_writelane_b32 v1, s75, 59
|
||||
; GCN-NEXT: v_writelane_b32 v1, s76, 60
|
||||
; GCN-NEXT: v_writelane_b32 v1, s77, 61
|
||||
; GCN-NEXT: v_writelane_b32 v1, s78, 62
|
||||
; GCN-NEXT: v_writelane_b32 v1, s79, 63
|
||||
; GCN-NEXT: v_writelane_b32 v2, s80, 0
|
||||
; GCN-NEXT: v_writelane_b32 v2, s81, 1
|
||||
; GCN-NEXT: v_writelane_b32 v2, s82, 2
|
||||
; GCN-NEXT: v_writelane_b32 v2, s83, 3
|
||||
; GCN-NEXT: v_writelane_b32 v2, s84, 4
|
||||
; GCN-NEXT: v_writelane_b32 v2, s85, 5
|
||||
; GCN-NEXT: v_writelane_b32 v2, s86, 6
|
||||
; GCN-NEXT: v_writelane_b32 v2, s87, 7
|
||||
; GCN: s_cbranch_scc1
|
||||
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v0, 0
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 1
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 2
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 3
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 4
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 5
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 6
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v0, 7
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 0
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 1
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 2
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 3
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 4
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 5
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 6
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 7
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 8
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 9
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 10
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 11
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 12
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 13
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 14
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 15
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 16
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 17
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 18
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 19
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 20
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 21
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 22
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 23
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 24
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 25
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 26
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 27
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 28
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 29
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 30
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 31
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 32
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 33
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 34
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 35
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 36
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 37
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 38
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 39
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 40
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 41
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 42
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 43
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 44
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 45
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 46
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 47
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 48
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 49
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 50
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 51
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 52
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 53
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 54
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 55
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 56
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 57
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 58
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 59
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 60
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 61
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 62
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 63
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v2, 0
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 1
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 2
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 3
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 4
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 5
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 6
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 7
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 56
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 57
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 58
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 59
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 60
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 61
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 62
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 63
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 8
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 9
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 10
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 11
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 12
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 13
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 14
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 15
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 16
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 17
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 18
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 19
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 20
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 21
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 22
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 23
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 24
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 25
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 26
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 27
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 28
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 29
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 30
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 31
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 32
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 33
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 34
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 35
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 36
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 37
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 38
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 39
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 40
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 41
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 42
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 43
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 44
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 45
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 46
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 47
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 48
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 49
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 50
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 51
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 52
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 53
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 54
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 55
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
define amdgpu_kernel void @spill_sgprs_to_multiple_vgprs(i32 addrspace(1)* %out, i32 %in) #0 {
|
||||
%wide.sgpr0 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr1 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr2 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr4 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr5 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr6 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr7 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr8 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr9 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr10 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr11 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr12 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr13 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr14 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr15 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr16 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
br i1 %cmp, label %bb0, label %ret
|
||||
|
||||
bb0:
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr0) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr1) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr2) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr3) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr4) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr5) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr6) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr7) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr8) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr9) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr10) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr11) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr12) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr13) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr14) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr15) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr16) #0
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Some of the lanes of an SGPR spill are in one VGPR and some forced
|
||||
; into the next available VGPR.
|
||||
|
||||
; GCN-LABEL: {{^}}split_sgpr_spill_2_vgprs:
|
||||
; GCN: def s[24:39]
|
||||
|
||||
; GCN: v_writelane_b32 v0, s24, 50
|
||||
; GCN-NEXT: v_writelane_b32 v0, s25, 51
|
||||
; GCN-NEXT: v_writelane_b32 v0, s26, 52
|
||||
; GCN-NEXT: v_writelane_b32 v0, s27, 53
|
||||
; GCN-NEXT: v_writelane_b32 v0, s28, 54
|
||||
; GCN-NEXT: v_writelane_b32 v0, s29, 55
|
||||
; GCN-NEXT: v_writelane_b32 v0, s30, 56
|
||||
; GCN-NEXT: v_writelane_b32 v0, s31, 57
|
||||
; GCN-NEXT: v_writelane_b32 v0, s32, 58
|
||||
; GCN-NEXT: v_writelane_b32 v0, s33, 59
|
||||
; GCN-NEXT: v_writelane_b32 v0, s34, 60
|
||||
; GCN-NEXT: v_writelane_b32 v0, s35, 61
|
||||
; GCN-NEXT: v_writelane_b32 v0, s36, 62
|
||||
; GCN-NEXT: v_writelane_b32 v0, s37, 63
|
||||
; GCN-NEXT: v_writelane_b32 v1, s38, 0
|
||||
; GCN-NEXT: v_writelane_b32 v1, s39, 1
|
||||
|
||||
; GCN: v_readlane_b32 s4, v0, 50
|
||||
; GCN-NEXT: v_readlane_b32 s5, v0, 51
|
||||
; GCN-NEXT: v_readlane_b32 s6, v0, 52
|
||||
; GCN-NEXT: v_readlane_b32 s7, v0, 53
|
||||
; GCN-NEXT: v_readlane_b32 s8, v0, 54
|
||||
; GCN-NEXT: v_readlane_b32 s9, v0, 55
|
||||
; GCN-NEXT: v_readlane_b32 s10, v0, 56
|
||||
; GCN-NEXT: v_readlane_b32 s11, v0, 57
|
||||
; GCN-NEXT: v_readlane_b32 s12, v0, 58
|
||||
; GCN-NEXT: v_readlane_b32 s13, v0, 59
|
||||
; GCN-NEXT: v_readlane_b32 s14, v0, 60
|
||||
; GCN-NEXT: v_readlane_b32 s15, v0, 61
|
||||
; GCN-NEXT: v_readlane_b32 s16, v0, 62
|
||||
; GCN-NEXT: v_readlane_b32 s17, v0, 63
|
||||
; GCN-NEXT: v_readlane_b32 s18, v1, 0
|
||||
; GCN-NEXT: v_readlane_b32 s19, v1, 1
|
||||
define amdgpu_kernel void @split_sgpr_spill_2_vgprs(i32 addrspace(1)* %out, i32 %in) #1 {
|
||||
%wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr2 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr5 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
br i1 %cmp, label %bb0, label %ret
|
||||
|
||||
bb0:
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr0) #0
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr1) #0
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr2) #0
|
||||
call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr3) #0
|
||||
call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr4) #0
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr5) #0
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
ret void
|
||||
}
|
||||
|
||||
; The first 64 SGPR spills can go to a VGPR, but there isn't a second
|
||||
; so some spills must be to memory. The last 16 element spill runs out of lanes at the 15th element.
|
||||
|
||||
; GCN-LABEL: {{^}}no_vgprs_last_sgpr_spill:
|
||||
|
||||
; GCN: v_writelane_b32 v23, s{{[0-9]+}}, 0
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 1
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 2
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 3
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 4
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 5
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 6
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 7
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 8
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 9
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 10
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 11
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 12
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 13
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 14
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 15
|
||||
|
||||
; GCN: v_writelane_b32 v23, s{{[0-9]+}}, 16
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 17
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 18
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 19
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 20
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 21
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 22
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 23
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 24
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 25
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 26
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 27
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 28
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 29
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 30
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 31
|
||||
|
||||
; GCN: def s[0:1]
|
||||
; GCN: v_writelane_b32 v23, s0, 32
|
||||
; GCN-NEXT: v_writelane_b32 v23, s1, 33
|
||||
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 34
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 35
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 36
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 37
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 38
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 39
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 40
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 41
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 42
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 43
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 44
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 45
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 46
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 47
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 48
|
||||
; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 49
|
||||
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: s_cbranch_scc1
|
||||
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v23, 0
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 1
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 2
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 3
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 4
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 5
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 6
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 7
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 8
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 9
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 10
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 11
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 12
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 13
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 14
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v23, 15
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v23, 34
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 35
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 36
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 37
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 38
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 39
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 40
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 41
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 42
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 43
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 44
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 45
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 46
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 47
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 48
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v23, 49
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v23, 16
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 17
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 18
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 19
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 20
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 21
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 22
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 23
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 24
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 25
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 26
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 27
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 28
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 29
|
||||
; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 30
|
||||
; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v23, 31
|
||||
; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}}
|
||||
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
|
||||
|
||||
; GCN: v_readlane_b32 s0, v23, 32
|
||||
; GCN: v_readlane_b32 s1, v23, 33
|
||||
; GCN: ;;#ASMSTART
|
||||
; GCN: ; use s[0:1]
|
||||
define amdgpu_kernel void @no_vgprs_last_sgpr_spill(i32 addrspace(1)* %out, i32 %in) #1 {
|
||||
call void asm sideeffect "", "~{VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7}" () #0
|
||||
call void asm sideeffect "", "~{VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15}" () #0
|
||||
call void asm sideeffect "", "~{VGPR16_VGPR17_VGPR18_VGPR19}"() #0
|
||||
call void asm sideeffect "", "~{VGPR20_VGPR21}"() #0
|
||||
call void asm sideeffect "", "~{VGPR22}"() #0
|
||||
|
||||
%wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr2 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr3 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%wide.sgpr4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
br i1 %cmp, label %bb0, label %ret
|
||||
|
||||
bb0:
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr0) #0
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr1) #0
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr2) #0
|
||||
call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr3) #0
|
||||
call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr4) #0
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" }
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
; RUN: llc -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=TOVGPR %s
|
||||
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling,-mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s
|
||||
|
||||
; These tests check that the compiler won't crash when it needs to spill
|
||||
; SGPRs.
|
||||
|
|
@ -17,10 +17,14 @@
|
|||
|
||||
; CHECK: s_mov_b32 m0
|
||||
|
||||
; Make sure scratch space isn't being used for SGPR->VGPR spills
|
||||
; FIXME: Seem to be leaving behind unused emergency slot.
|
||||
|
||||
; Writing to M0 from an SMRD instruction will hang the GPU.
|
||||
; CHECK-NOT: s_buffer_load_dword m0
|
||||
; CHECK: s_endpgm
|
||||
|
||||
; TOVGPR: ScratchSize: 4{{$}}
|
||||
define amdgpu_ps void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
|
||||
main_body:
|
||||
%tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0
|
||||
|
|
@ -768,6 +772,7 @@ ENDIF66: ; preds = %LOOP65
|
|||
|
||||
; CHECK-LABEL: {{^}}main1:
|
||||
; CHECK: s_endpgm
|
||||
; TOVGPR: ScratchSize: 4{{$}}
|
||||
define amdgpu_ps void @main1([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
|
||||
main_body:
|
||||
%tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue