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Remove redundand register move 

llvm-svn: 76004
This commit is contained in:
Anton Korobeynikov 2009-07-16 14:14:54 +00:00
parent fe8df8ff61
commit e0ad108f04
2 changed files with 15 additions and 21 deletions
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28
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -645,7 +645,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
default: assert(0 && "Unsupported VT!"); default: assert(0 && "Unsupported VT!");
case MVT::i32: case MVT::i32:
Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
ClrOpc = SystemZ::MOV32ri16; ClrOpc = SystemZ::MOV64Pr0_even;
ResVT = MVT::v2i32; ResVT = MVT::v2i32;
break; break;
case MVT::i64: case MVT::i64:
@ -669,15 +669,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
CurDAG->getTargetConstant(subreg_odd, MVT::i32)); CurDAG->getTargetConstant(subreg_odd, MVT::i32));
// Zero out even subreg, if needed // Zero out even subreg, if needed
if (ClrOpc) { if (ClrOpc)
SDNode * ZeroHi = CurDAG->getTargetNode(SystemZ::MOV32ri16, dl, NVT, Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
CurDAG->getTargetConstant(0, MVT::i32));
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Dividend, 0),
SDValue(ZeroHi, 0),
CurDAG->getTargetConstant(subreg_even, MVT::i32));
}
SDNode *Result; SDNode *Result;
SDValue DivVal = SDValue(Dividend, 0); SDValue DivVal = SDValue(Dividend, 0);
@ -736,12 +729,12 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
default: assert(0 && "Unsupported VT!"); default: assert(0 && "Unsupported VT!");
case MVT::i32: case MVT::i32:
Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
ClrOpc = SystemZ::MOV32ri16; ClrOpc = SystemZ::MOV64Pr0_even;
ResVT = MVT::v2i32; ResVT = MVT::v2i32;
break; break;
case MVT::i64: case MVT::i64:
Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
ClrOpc = SystemZ::MOV64ri16; ClrOpc = SystemZ::MOV128r0_even;
ResVT = MVT::v2i64; ResVT = MVT::v2i64;
break; break;
} }
@ -760,15 +753,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
SDValue(Tmp, 0), SDValue(Dividend, 0), SDValue(Tmp, 0), SDValue(Dividend, 0),
CurDAG->getTargetConstant(subreg_odd, MVT::i32)); CurDAG->getTargetConstant(subreg_odd, MVT::i32));
// Zero out even subreg, if needed // Zero out even subreg
SDNode * ZeroHi = CurDAG->getTargetNode(ClrOpc, dl, NVT, Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
CurDAG->getTargetConstant(0,
MVT::i32));
Dividend =
CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
SDValue(Dividend, 0),
SDValue(ZeroHi, 0),
CurDAG->getTargetConstant(subreg_even, MVT::i32));
SDValue DivVal = SDValue(Dividend, 0); SDValue DivVal = SDValue(Dividend, 0);
SDNode *Result; SDNode *Result;

8
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -370,6 +370,14 @@ def MOV64rmm : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
"lmg\t{$from, $to, $dst}", "lmg\t{$from, $to, $dst}",
[]>; []>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
"lhi\t${dst:subreg_even}, 0",
[]>;
def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
"lghi\t${dst:subreg_even}, 0",
[]>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Arithmetic Instructions // Arithmetic Instructions