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Use a combination of copyRegToReg and ISD::BIT_CONVERT when doing fast isel of bitcasts, 

allowing it to support the full range of conversions people might ask for in a correct manner.

llvm-svn: 55378
This commit is contained in:
Owen Anderson 2008-08-26 18:51:24 +00:00
parent 42ccd39689
commit e0ac9765b2
1 changed files with 19 additions and 8 deletions
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21
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
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@ -251,19 +251,30 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
// Unhandled type. Halt "fast" selection and bail. // Unhandled type. Halt "fast" selection and bail.
return I; return I;
// Otherwise, insert a register-to-register copy.
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
unsigned Op0 = ValueMap[I->getOperand(0)]; unsigned Op0 = ValueMap[I->getOperand(0)];
unsigned ResultReg = createResultReg(DstClass);
if (Op0 == 0) if (Op0 == 0)
// Unhandled operand. Halt "fast" selection and bail. // Unhandled operand. Halt "fast" selection and bail.
return false; return false;
// First, try to perform the bitcast by inserting a reg-reg copy.
unsigned ResultReg = 0;
if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
ResultReg = createResultReg(DstClass);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
Op0, DstClass, SrcClass); Op0, DstClass, SrcClass);
if (!InsertedCopy) if (!InsertedCopy)
ResultReg = 0;
}
// If the reg-reg copy failed, select a BIT_CONVERT opcode.
if (!ResultReg)
ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
ISD::BIT_CONVERT, Op0);
if (!ResultReg)
return I; return I;
ValueMap[I] = ResultReg; ValueMap[I] = ResultReg;